AUTOMATIC GENERATION OF POWER MANAGEMENT SEQUENCE IN A SOC OR NOC
Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.
1 . A System on Chip (SoC), comprising:
at least one first hardware element configured to consume data from at least one second hardware element configured to provide data, the first hardware element configured to be rendered inactive in response to a signal;
wherein the at least one second hardware element, in response to sending the data to the at least one first hardware element when the at least one first hardware element is rendered inactive, is configured to conduct error handling.
2 . The SoC of claim 1 , wherein the error handling comprises sending an instruction to the at least one first hardware element to render the at least one first hardware element as active.
3 . A Network on Chip (NoC), comprising:
at least one first hardware element configured to consume data from at least one second hardware element configured to provide data, the first hardware element configured to be rendered inactive in response to a signal;
wherein the at least one second hardware element, in response to sending the data to the at least one first hardware element when the at least one first hardware element is rendered inactive, is configured to conduct error handling.
4 . The NoC of claim 3 , wherein the error handling comprises sending an instruction to the at least one first hardware element to render the at least one first hardware element as active.