System level simulation in network on chip architecture
View Patent ↗Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC behavior are described. The example implementations involve simulations to evaluate and detect NoC behavior based on execution of multiple transactions at different rates/times/intervals, wherein each transaction can contain one or more messages, with each message being associated with a source agent and a destination agent. Each message can also be associated with multiple parameters such as rate, size, value, latency, among other like parameters that can be configured to indicate the execution of the transaction by a simulator to simulate a real-time scenario for generating performance reports for the NoC interconnect.
1. A method, comprising:
performing, on a computer, a simulation of a Network-on-Chip (NoC) interconnect by using a plurality of transactions, wherein each of the plurality of transactions comprises a sequence of one or more messages, and wherein each of the one or more messages comprises an indication for at least one of a source and a destination agent; and
generating subsequent messages in the sequence of the one or more messages for ones of the plurality of transactions based on a first message destination node in the sequence of the one or more messages, wherein the subsequent messages are generated at each destination node of the one or more messages.
2. The method of claim 1 , wherein each of the one or more messages comprises an indication for at least one of a rate, a priority, a value, a message data size, latency, and an interval, and wherein messages are used for performing the simulation based on at least one of the rate, the priority, the value, the message data size, the latency and the interval.
3. The method of claim 2 , wherein the each of the one or more messages comprises an indication for a rate, wherein the rate comprises an indication of a probability of selection of a respective message during the simulation.
4. The method of claim 1 , further comprising generating a trace file for each agent based on the ones of the plurality of transaction sequences that originate from the each agent, wherein the trace file comprises a subset of the one or more messages in the ones of the plurality of transaction sequences.
5. The method of claim 1 , further comprising generating a performance report of the NoC interconnect based on the simulation.
6. A server, comprising:
a processor configured to:
perform a simulation of a Network-on-Chip (NoC) interconnect by using a plurality of transactions, wherein each of the plurality of transaction sequences comprises a sequence of one or more messages, and wherein each of the one or more messages comprises an indication for at least one of a source and a destination agent; and
generate subsequent messages in the sequence of the one or more messages for ones of the plurality of transactions based on a first message destination node in the sequence of the one or more messages, wherein the subsequent messages are generated at each destination node of the one or more messages.
7. The server of claim 6 , wherein each of the one or more messages comprises an indication for at least one of a rate, a priority, a value, a message data size, latency, and an interval, and wherein messages are used for performing the simulation based on at least one of the rate, the priority, the value, the message data size, the latency and the interval.
8. The server of claim 7 , wherein the each of the one or more messages comprises an indication for a rate, wherein the rate comprises an indication of a probability of selection of a respective message during the simulation.
9. The server of claim 6 , wherein the processor is configured to generate a trace file for each agent based on the ones of the plurality of transaction sequences that originate from the each agent, wherein the trace file comprises an indication of the one or more messages for each of the plurality of transaction sequences.
10. The server of claim 6 , wherein the processor is further configured to generate a performance report of the NoC interconnect based on the simulation.