Asymmetric mesh NoC topologies
View Patent ↗Example implementations described herein are directed to a system on chip (SoC) that can include a plurality of blocks of substantially non-uniform shapes and dimensions, a plurality of routers, and a plurality of links between routers. The plurality of blocks and the plurality of routers are interconnected by the plurality of links using a Network-on-Chip (NoC) architecture with a sparse mesh topology. The sparse mesh topology involves a sparsely populated mesh which is a subset of a full mesh having one or more of the plurality of routers or links removed. The plurality of blocks communicate among each other by routing messages over the remaining ones of the plurality of routers and links of the sparse mesh.
1. A system on chip, comprising:
a plurality of blocks of substantially non-uniform shapes and dimensions;
a plurality of routers; and
a plurality of links between routers,
wherein the plurality of blocks and the plurality of routers are interconnected by the plurality of links using a Network-on-Chip architecture with a sparse mesh topology, and
wherein the sparse mesh topology comprises a sparsely populated mesh which is a subset of a full mesh having one or more of the plurality of routers or links removed, and
wherein the plurality of blocks communicate among each other by routing messages over the remaining ones of the plurality of routers and links of the sparse mesh.