INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP
Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.
1 . A hardware element incorporated into a Network on Chip (NoC), comprising:
a plurality of physical links and virtual links;
a queue for transmission of output messages to output ports of the hardware element;
an arbiter configured to process input messages to the queue based on a logic scheme;
a configurable bypass link between the virtual links, and
bypass logic configured to redirect the input messages to the configurable bypass link to bypass the queue and the arbiter.
2 . The hardware element of claim 1 , wherein the bypass logic is configured to redirect the input messages to the configurable bypass link opportunistically.
3 . A hardware element incorporated into a System on Chip (SoC), comprising:
a plurality of physical links and virtual links;
a queue for transmission of output messages to output ports of the hardware element;
an arbiter configured to process input messages to the queue based on a logic scheme;
a configurable bypass link between the virtual links, and
bypass logic configured to redirect the input messages to the configurable bypass link to bypass the queue and the arbiter.
4 . The hardware element of claim 3 , wherein the bypass logic is configured to redirect the input messages to the configurable bypass link opportunistically.