IP Library Granted Patent US 10,050,843
Granted Patent B2
US 10,050,843 · App. 14/625,132 · Granted Aug 14, 2018

Generation of network-on-chip layout based on user specified topological constraints

Inventors: Pier Giorgio Raponi (San Jose, CA); Eric Norige (San Jose, CA); Sailesh Kumar (San Jose, CA)
Assignee: NetSpeed Systems
H04L41/145G06F17/50H04L41/12
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Quick Facts
Patent No.
US 10,050,843
App. No.
14/625,132
Granted
Aug 14, 2018
Kind
B2
Abstract

In an aspect, the present disclosure provides a method that comprises automatic generation of a NoC from specified topological information based on projecting NoC elements of the NoC onto a grid layout. In an aspect, the specified topological information, including specification of putting constraints on positions/locations of NoC elements and links thereof, can be input by a user in real space, and can then be projected on the grid layout.

Claims (17)

1. A method, comprising:

projecting Network on Chip (NoC) elements of a NoC to a grid layout based on specified topological information; and

automatically generating the NoC from the projection of the NoC elements to the grid layout;

wherein the projecting NoC elements of the NoC to the grid layout based on the specified topological information comprises:

projecting a plurality of nodes, a plurality of routers and a plurality of links onto the grid layout based on the specified topological information, wherein the projected plurality of routers, the plurality of nodes, and the plurality of links are disabled;

selectively enabling ones of the plurality of routers, ones of the plurality of nodes, and ones of the plurality of links on the grid layout based on one or more constraints for one or more layers of the NoC;

providing NoC agents on enabled ones of the plurality of nodes of the grid layout;

providing traffic between the provided NoC agents; and

mapping the traffic to the enabled ones of the plurality of routers and the plurality of links of the NoC.

2. A non-transitory computer readable medium, storing instructions for executing a process, the instructions comprising:

projecting Network on Chip (NoC) elements of a NoC to a grid layout based on specified topological information; and

automatically generating the NoC from the projection of the NoC elements to the grid layout;

wherein the projecting NoC elements of the NoC to the grid layout based on the specified topological information comprises:

projecting a plurality of nodes, a plurality of routers and a plurality of links onto the grid layout based on the specified topological information, wherein the projected plurality of routers, the plurality of nodes, and the plurality of links are disabled;

selectively enabling ones of the plurality of routers, ones of the plurality of nodes, and ones of the plurality of links on the grid layout based on one or more constraints for one or more layers of the NoC;

providing NoC agents on enabled ones of the plurality of nodes of the grid layout providing traffic between the provided NoC agents; and

mapping the traffic to the enabled ones of the plurality of routers and the plurality of links of the NoC.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2022
From: NETSPEED SYSTEMS, INC.
To: INTEL CORPORATION
Reel/Frame 060753/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2015
From: RAPONI, PIER GIORGIO; NORIGE, ERIC; KUMAR, SAILESH
To: NETSPEED SYSTEMS
Reel/Frame 035033/0171 →
Continuity (1)
Related Publication 20170063639A1 · Mar 2, 2017
Cited By (1)
US 12,327,077