SYSTEMS AND METHODS FOR MAINTAINING NETWORK-ON-CHIP (NOC) SAFETY AND RELIABILITY
Methods and example implementations described herein are directed to systems and methods for maintaining network-on-chip (NoC) safety and reliability. An aspect of the present disclosure relates to an network-on-chip (NoC)-based error correction system capable of supporting a network interface (NI) that transmits a flit between a transmission side (Tx) intellectual property (IP) element and a receiving side (Rx) IP element. The system includes an encoder configured to receive a k-bit flit from the Tx IP element and encodes the k-bit flit into n-bit data (where k and n denote any natural numbers), and a decoder configured to receive the n-bit data, decode the n-bit data into the k-bit flit, and output the k-bit flit, the decoder having an error correction circuit for correcting an error in the n-bit data. In an aspect, the error correction circuit comprises a multiple overlapping layers of coverage configured for the NoC transport infrastructure.
1 . An network-on-chip (NoC)-based error correction system capable of supporting a network interface (NI) that transmits a flit between a transmission side (Tx) intellectual property (IP) element and a receiving side (Rx) IP element, the system comprising:
an encoder configured to receive a k-bit flit from the Tx IP element and encodes the k-bit flit into n-bit data (where k and n denote any natural numbers);
a decoder configured to receive the n-bit data, decode the n-bit data into the k-bit flit, and output the k-bit flit, the decoder having an error correction circuit for correcting an error in the n-bit data, wherein the error correction circuit comprises a multiple overlapping layers of coverage configured for the NoC transport infrastructure.
2 . The NoC-based error correction system of claim 1 , wherein the error correction circuit comprises a transport error detection and correction mechanism.
3 . The NoC-based error correction system of claim 1 , wherein the error correction circuit comprises an end to end transport error checking mechanism.
4 . The NoC-based error correction system of claim 3 , wherein the end to end transport error checking mechanism includes any or combination of data protection Per flit ECC, data error detection Per flit parity, data protection transport of user provided ECC, and sideband protection: ECC or Parity.
5 . The NoC-based error correction system of claim 1 , wherein the error correction circuit comprises a hop to hop Error checking mechanism.
6 . The NoC-based error correction system of claim 5 , wherein the hop to hop Error checking mechanism includes any or combination of protection of packet control fields, error detection using e2e ECC/Parity, and implementation of parity check.
7 . The NoC-based error correction system of claim 1 , wherein the error correction circuit comprises an end to end packet integrity mechanism.
8 . The NoC-based error correction system of claim 7 , wherein the end packet integrity mechanism includes any or combination of detecting misrouted packets, detecting bit interleaved parity, and detecting Flit ID.
9 . The NoC-based error correction system of claim 1 , wherein the error correction circuit comprises an end to end packet stream integrity mechanism.
10 . A method for supporting a network interface (NI) that transmits a flit between a transmission side (Tx) intellectual property (IP) element and a receiving side (Rx) IP element, comprising:
receiving, by an encoder, a k-bit flit from the Tx IP element and encodes the k-bit flit into n-bit data (where k and n denote any natural numbers); and
receiving, by a decoder, the n-bit data, decode the n-bit data into the k-bit flit, and output the k-bit flit, the decoder having an error correction circuit for correcting an error in the n-bit data, wherein the error correction circuit comprises a multiple overlapping layers of coverage configured for the NoC transport infrastructure.
11 . The method of claim 11 , wherein the error correction circuit comprises a transport error detection and correction mechanism.
12 . The method of claim 11 , wherein the error correction circuit comprises an end to end transport error checking mechanism.
13 . The method of claim 14 , wherein the end to end transport error checking mechanism includes any or combination of data protection Per flit ECC, data error detection Per flit parity, data protection transport of user provided ECC, and sideband protection: ECC or Parity.
14 . The method of claim 11 , wherein the error correction circuit comprises a hop to hop Error checking mechanism.
15 . The method of claim 14 , wherein the hop to hop Error checking mechanism includes any or combination of protection of packet control fields, error detection using e2e ECC/Parity, and 1.3.3 Implementation of parity check.
16 . The method of claim 11 , wherein the error correction circuit comprises an end to end packet integrity mechanism.
17 . The method of claim 16 , wherein the end packet integrity mechanism includes any or combination of detecting misrouted packets, detecting bit interleaved parity, and detecting Flit ID.
18 . The method of claim 11 , wherein the error correction circuit comprises an end to end packet stream integrity mechanism.