Automatic pipelining of NoC channels to meet timing and/or performance
View Patent ↗Systems and methods for automatically generating a Network on Chip (NoC) interconnect architecture with pipeline stages are described. The present disclosure includes example implementations directed to automatically determining the number and placement of pipeline stages for each channel in the NoC. Example implementations may also adjust the buffer at one or more routers based on the pipeline stages and configure throughput for virtual channels.
1. A method, comprising:
generating a Network on Chip (NoC) comprising a plurality of channels and a plurality of routers, the NoC configured with one or more pipeline stages that are positioned at one or more of the plurality of channels in the NoC based on an associated system on chip (SoC) floorplan and a NoC topology;
for each of the plurality of channels in the NoC, generating an output register for a corresponding one of the plurality of routers handling output for the each of the one or more channels in the NoC based on a setup time of the corresponding router and a timing path within the corresponding router; and
configuring a physical SoC with the generated NoC and generated output registers.
2. The method of claim 1 , further comprising:
determining a number of the one or more pipeline stages for each of the plurality of channels in the NoC based on a clock frequency between a pair of the plurality of routers associated with the each of the one or more channels and a length of the each of the one or more channels, and
generating the one or more pipeline stages for the each of the plurality of channels based on the number determined by the determining.
3. The method of claim 2 , further comprising positioning each of the generated one or more pipeline stages for the each of the plurality of channels based on a wire delay of the each of the plurality of channels.
4. The method of claim 2 , further comprising adjusting a buffer at each of the plurality of routers based on the number of the one or more pipeline stages between a pairing of the each of the plurality of routers with an adjacent one of the plurality of routers.
5. The method of claim 4 , wherein adjusting the buffer at each of the plurality of routers is further based on a throughput requirement between the pairing of the each of the plurality of routers with the adjacent one of the plurality of routers.
6. The method of claim 5 , further comprising sizing one or more virtual channels associated with the each of the plurality of routers based on the throughput requirement.
7. The method of claim 4 , wherein each of the one or more pipeline stages is configured to be utilized as a buffer supplement, and wherein the adjusting the buffer at each of the plurality of routers is based on ones of the one or more pipeline stages utilized by the each of the plurality of routers as a buffer supplement.
8. A non-transitory computer readable storage medium storing instructions for executing a process, the instructions comprising:
generating a Network on Chip (NoC) comprising a plurality of channels and a plurality of routers, the NoC configured with one or more pipeline stages that are positioned at one or more of the plurality of channels in the NoC based on an associated system on chip (SoC) floorplan and a NoC topology;
for each of the plurality of channels in the NoC, generating an output register for a corresponding one of the plurality of routers handling output for the each of the one or more channels in the NoC based on a setup time of the corresponding router and a timing path within the corresponding router; and
configuring a physical SoC with the generated NoC and generated output registers.
9. The non-transitory computer readable storage medium of claim 8 , wherein the instructions further comprise:
determining a number of the one or more pipeline stages for each of the plurality of channels in the NoC based on a clock frequency between a pair of the plurality of routers associated with the each of the one or more channels and a length of the each of the one or more channels, and
generating the one or more pipeline stages for the each of the plurality of channels based on the number.
10. The non-transitory computer readable storage medium of claim 9 , wherein the instructions further comprise positioning each of the generated one or more pipeline stages for the each of the plurality of channels based on a wire delay of the each of the plurality of channels.
11. The non-transitory computer readable storage medium of claim 9 , wherein the instructions further comprise adjusting a buffer at each of the plurality of routers based on the number of the one or more pipeline stages between a pairing of the each of the plurality of routers with an adjacent one of the plurality of routers.
12. The non-transitory computer readable storage medium of claim 11 , wherein adjusting the buffer at each of the plurality of routers is further based on a throughput requirement between the pairing of the each of the plurality of routers with the adjacent one of the plurality of routers.
13. The non-transitory computer readable storage medium of claim 12 , wherein the instructions further comprise sizing one or more virtual channels associated with the each of the plurality of routers based on the throughput requirement.
14. The non-transitory computer readable storage medium of claim 11 , wherein each of the one or more pipeline stages is configured to be utilized as a buffer supplement, and wherein the adjusting the buffer at each of the plurality of routers is based on ones of the one or more pipeline stages utilized by the each of the plurality of routers as a buffer supplement.