Laterally diffused metal oxide semiconductor device and method of forming the same
View Patent ↗A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.
1. A method of forming a transistor, comprising:
providing a semiconductor substrate;
forming a gate on said semiconductor substrate;
forming a source/drain by:
forming a lightly doped region adjacent a channel region recessed into said semiconductor substrate, and
forming a heavily doped region adjacent said lightly doped region;
forming an oppositely doped well under and within said channel region; and
forming a doped region between said heavily doped region and said oppositely doped well without surrounding said lightly doped region, said doped region having a doping concentration profile less than a doping concentration profile of said heavily doped region.
2. The method as recited in claim 1 further comprising forming an oppositely doped buried layer recessed into said substrate.
3. The method as recited in claim 1 further comprising forming an epitaxial layer over said semiconductor substrate, said doped region being formed from said epitaxial layer.
4. The method as recited in claim 1 wherein said source/drain includes P-type lightly and heavily doped regions and said oppositely doped well is an N-type well, said doped region being a P-type doped region having a doping concentration profile less than a doping concentration profile of said P-type heavily doped region.
5. The method as recited in claim 1 , further comprising:
forming another source/drain by:
forming a lightly doped region located adjacent said channel region, and
forming a heavily doped region located adjacent said lightly doped region; and
forming another doped region between said heavily doped region of said another source/drain and said oppositely doped well, said another doped region having a doping concentration profile less than a doping concentration profile of said heavily doped region of said another source/drain.
6. The method as recited in claim 1 , further comprising:
forming a gate dielectric layer over said semiconductor substrate;
forming gate sidewall spacers about said gate;
forming a salicide layer on said gate and said source/drain; and
forming metal contacts over said salicide layer on said gate and said source/drain.
7. The method as recited in claim 1 wherein said heavily doped region is adjacent to but not surrounded by said lightly doped region.
8. The method as recited in claim 1 wherein said heavily doped region is located on a side opposite said channel region to said lightly doped region.
9. The method as recited in claim 1 further comprising forming an isolation region adjacent said heavily doped region opposite said lightly doped region within said semiconductor substrate.
10. The method as recited in claim 1 wherein said doping concentration profile of said doped well is different from a doping concentration profile of said lightly doped region.