Apparatus and methods for adjusting performance of integrated circuits
View Patent ↗A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
1. A programmable logic device (PLD), comprising:
a delay circuit, the delay circuit having a delay configured to represent a delay of a user circuit implemented in the programmable logic device (PLD), the delay circuit comprising at least one logic delay element and at least one routing delay element implemented using programmable circuitry in the PLD; and
a body-bias generator, the body-bias generator configured to adjust a body bias of a transistor within the user circuit in response to a level derived from a propagation delay of the delay circuit.
2. The programmable logic device (PLD) according to claim 1 , wherein the delay circuit comprises combinational logic.
3. The programmable logic device (PLD) according to claim 1 , further comprising a phase comparator, the phase comparator configured to compare a phase of an output signal of the delay circuit in response to a reference signal applied to an input of the delay circuit, and a phase of the reference signal.
4. The programmable logic device (PLD) according to claim 3 , wherein the comparator is further configured to provide a first output signal and a second output signal.
5. The programmable logic device (PLD) according to claim 4 , wherein, in response to the first output signal, the body-bias generator adjusts the body bias of the transistor so as to speed up an operation of the transistor.
6. The programmable logic device (PLD) according to claim 4 , wherein, in response to the second output signal, the body-bias generator adjusts the body bias of the transistor so as to slow down an operation of the transistor.
7. The programmable logic device (PLD) according to claim 3 , wherein the delay circuit comprises a configurable delay circuit.
8. The programmable logic device (PLD) according to claim 7 , wherein the propagation delay of the configurable delay circuit is configurable.
9. The programmable logic device (PLD) according to claim 1 , wherein the user circuit comprises at least one programmable logic element and at least one programmable interconnect element.