Patent Assignment
Reel/Frame 060778/0032
Assignment of Assignor's Interest
Recorded: 2022-07-20
Pages: 32
Assignor
ALTERA CORPORATION
Executed: 2022-07-08
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(434)
Clock Signal Circuitry for Multi-Protocol High-Speed Serial Interface Circuitry
Patent:
7,180,972 →
Application:
10/273,899 →
Pld Debugging Hub
Logic Circuitry with Shared Lookup Table
Patent:
6,798,240 →
Application:
10/351,026 →
Interface for a Programmable Logic Device
Patent:
6,894,531 →
Application:
10/444,741 →
Programmable Logic Device Serial Interface Having Dual-Use Phase-Locked Loop Circuitry
Patent:
6,867,616 →
Application:
10/455,773 →
Selectable Dynamic Reconfiguration of Programmable Embedded Ip
Patent:
6,842,034 →
Application:
10/612,253 →
Low Warpage Flip Chip Package Solution-Channel Heat Spreader
Patent:
6,888,238 →
Application:
10/616,858 →
Embedded Microprocessor for Integrated Circuit Testing and Debugging
Patent:
7,539,900 →
Application:
10/629,508 →
Electrically-Programmable Integrated Circuit Antifuses
Patent:
6,897,543 →
Application:
10/646,013 →
Functional Pre-Configuration of a Programmable Logic Device
Patent:
7,030,646 →
Application:
10/654,518 →
Adjustable Differential Input and Output Drivers
Patent:
6,864,704 →
Application:
10/669,298 →
Dynamically-Adjustable Differential Output Drivers
Patent:
6,943,588 →
Application:
10/670,146 →
Apparatus and Methods for Shared Memory Interfaces in Programmable Logic Devices
Patent:
6,828,822 →
Application:
10/678,798 →
Programmable Phase-Locked Loop Circuitry for Programmable Logic Device
Programmable Logic Resource with Data Transfer Synchronization
Patent:
7,003,423 →
Application:
10/741,593 →
Programmable Logic Device with on-Chip Nonvolatile User Memory
Patent:
7,190,190 →
Application:
10/754,432 →
Adaptive Compression and Decompression of Bandlimited Signals
Patent:
7,009,533 →
Application:
10/778,880 →
Enhanced Data Converters Using Compression and Decompression
Patent:
7,088,276 →
Application:
10/778,881 →
Multiplier-Accumulator Block Mode Splitting
Saturation and Rounding in Multiply-Accumulate Blocks
Programmable Logic Device Having Nonvolatile Memory with User Selectable Power Consumption
Patent:
6,853,603 →
Application:
10/797,493 →
Highly Configurable Pll Architecture for Programmable Logic
Integrated Circuits with Temperature-Change and Threshold-Voltage Drift Compensation
Patent:
6,933,869 →
Application:
10/802,590 →
Omnibus Logic Element Including Look Up Table Based Logic Elements
Patent:
7,167,022 →
Application:
10/810,117 →
Bit Slip Circuitry for Serial Data Signals
Patent:
7,440,532 →
Application:
10/830,277 →
Configurable Clock Network for Programmable Logic Device
Patent:
7,075,365 →
Application:
10/830,562 →
Apparatus and Methods for Adjusting Performance of Programmable Logic Devices
Apparatus and Methods for Multi-Gate Silicon-on-Insulator Transistors
Patent:
7,112,997 →
Application:
10/849,074 →
Generating Optimized and Secure Ip Cores
Patent:
7,165,229 →
Application:
10/852,832 →
Techniques for Reducing Power Consumption in Memory Cells
Patent:
6,972,987 →
Application:
10/856,187 →
Memory Interface Phase-Shift Circuitry to Support Multiple Frequency Ranges
Patent:
7,126,399 →
Application:
10/857,221 →
Multiple Data Rate Memory Interface Architecture
Patent:
7,176,714 →
Application:
10/857,396 →
Debuggable Opaque Ip
Patent:
7,409,652 →
Application:
10/861,893 →
Apparatus and Methods for Adjusting Performance of Integrated Circuits
Vpa Logic Circuits
Patent:
7,193,432 →
Application:
10/882,579 →
Configurable Circuits, Ic's, and Systems
Patent:
7,157,933 →
Application:
10/882,583 →
Configurable Logic Circuits with Commutative Properties
Patent:
7,126,373 →
Application:
10/882,839 →
Configurable Circuits, Ic's, and Systems
Patent:
7,193,440 →
Application:
10/882,946 →
Non-Sequentially Configurable Ic
Patent:
7,167,025 →
Application:
10/883,051 →
Vpa Interconnect Circuit
Patent:
7,126,381 →
Application:
10/883,213 →
Configurable Circuits, Ic's, and Systems
Patent:
7,109,752 →
Application:
10/883,276 →
Configurable Circuits, Ic's, and Systems
Logic Circuitry with Shared Lookup Table
Programmable Low-Voltage Differential Signaling Output Driver
Patent:
7,236,018 →
Application:
10/937,518 →
Adaptive Power Supply Voltage Regulation for Programmable Logic
Patent:
7,142,009 →
Application:
10/942,692 →
Next Generation 8B10B Architecture
Selectable Dynamic Reconfiguration of Programmable Embedded Ip
Patent:
7,071,726 →
Application:
11/005,390 →
Apparatus and methods for adjusting performance characteristics of programmable logic devices
Application:
11/006,420 →
Publication:
US 2006/0119382
Adjustable Differential Input and Output Drivers
Patent:
6,972,588 →
Application:
11/029,275 →
High-Performance Memory Interface Circuit Architecture
Patent:
7,227,395 →
Application:
11/055,125 →
Selectable Inversion of Differential Input and/or Output Pins in Programmable Logic Devices
Patent:
7,242,221 →
Application:
11/056,442 →
Method and System for Using Boundary Scan in a Programmable Logic Device
Patent:
7,248,070 →
Application:
11/059,929 →
Electrically-Programmable Integrated Circuit Antifuses
Patent:
7,272,067 →
Application:
11/060,925 →
Method and Apparatus for Accessing Contents of Memory Cells
Patent:
7,230,869 →
Application:
11/081,870 →
Method and Apparatus for Reduced Power Cell
Patent:
7,272,031 →
Application:
11/081,874 →
Modular Processor Debug Core Connection for Programmable Chip Systems
Patent:
7,627,784 →
Application:
11/101,027 →
Low Warpage Flip Chip Package Solution-Channel Heat Spreader
Interface for a Programmable Logic Device
Patent:
7,245,147 →
Application:
11/119,375 →
Programmable Phase-Locked Loop Circuitry for Programmable Logic Device
Dynamically-Adjustable Differential Output Drivers
Patent:
7,397,270 →
Application:
11/138,919 →
Method and System for Improving Memory Interface Data Integrity in Plds
Patent:
7,102,544 →
Application:
11/142,732 →
Charge Pump with Reduced Current Mismatch
Patent:
7,385,429 →
Application:
11/142,880 →
Adjustable Differential Input and Output Drivers
Patent:
7,245,144 →
Application:
11/169,242 →
Dynamic Frequency Divider with Improved Leakage Tolerance
Patent:
7,453,294 →
Application:
11/169,955 →
Volatile Memory Elements with Elevated Power Supply Levels for Programmable Logic Device Integrated Circuits
Configurable Clock Network for Programmable Logic Device
Patent:
7,286,007 →
Application:
11/282,876 →
Programmable Logic Device with Differential Communications Support
Patent:
7,505,331 →
Application:
11/286,165 →
Ball Grid Array Package-to-Board Interconnect Co-Design Apparatus
Patent:
7,405,477 →
Application:
11/292,685 →
User Registers Implemented with Routing Circuits in a Configurable Ic
Patent:
7,679,401 →
Application:
11/292,952 →
Users Registers in a Reconfigurable Ic
Patent:
7,489,162 →
Application:
11/293,856 →
Using Dedicated Read Output Path to Reduce Unregistered Read Access Time for Fpga Embedded Memory
Patent:
7,414,916 →
Application:
11/303,734 →
Apparatus and Methods for Power Management in Integrated Circuits
Method of Reducing Leakage Current Using Sleep Transistors in Programmable Logic Device
Patent:
7,355,440 →
Application:
11/318,324 →
Distributed Memory in Field-Programmable Gate Array Integrated Circuit Devices
Functional Pre-Configuration of a Programmable Logic Device
Patent:
7,498,837 →
Application:
11/347,469 →
Dedicated Resource Interconnects
Patent:
7,368,942 →
Application:
11/351,882 →
Apparatus and Methods for Adjusting Performance of Programmable Logic Devices
Adjustable Transistor Body Bias Generation Circuitry with Latch-Up Prevention
Latch-Up Prevention Circuitry for Integrated Circuits with Transistor Body Biasing
System and Method for Providing More Logical Memory Ports Than Physical Memory Ports
Patent:
7,797,497 →
Application:
11/371,214 →
Booting Mechanism for Fpga-Based Embedded System
Patent:
7,822,958 →
Application:
11/372,532 →
Configurable Ic with Packet Switch Configuration Network
Patent:
7,375,550 →
Application:
11/375,362 →
Configuration Network for a Configurable Ic
Runtime Loading of Configuration Data in a Configurable Ic
Configurable Ic with Trace Buffer and/or Logic Analyzer Functionality
Checkpointing User Design States in a Configurable Ic
Random Access of User Design States in a Configurable Ic
Accessing Multiple User States Concurrently in a Configurable Ic
Programmable Phase-Locked Loop Circuitry for Programmable Logic Device
Techniques for Providing Flexible on-Chip Termination Control on Integrated Circuits
Techniques for Sensing Temperature and Automatic Calibration on Integrated Circuits
Patent:
7,410,293 →
Application:
11/383,937 →
Flexible Ram Clock Enable
Patent:
7,397,726 →
Application:
11/399,771 →
Heterogeneous Transceiver Architecture for Wide Range Programmability of Programmable Logic Devices
Apparatus and Methods for Adjusting Performance Characteristics of Circuitry in Programmable Logic Devices
Application:
11/420,736 →
Publication:
US 2006/0202713
Apparatus and Methods for Adjusting Performance Characteristics and Power Consumption of Programmable Logic Devices
Adder-Rounder Circuitry for Specialized Processing Block in Programmable Logic Device
Patent:
7,822,799 →
Application:
11/426,403 →
Dc Output Voltage Circuit with Substantially Flat Psrr
Patent:
7,471,138 →
Application:
11/431,340 →
Voltage-Controlled Oscillator Methods and Apparatus
Patent:
7,728,674 →
Application:
11/437,558 →
Voltage regulator with high noise rejection
Application:
11/441,849 →
Specialized Processing Block for Programmable Logic Device
Specialized Processing Block for Programmable Logic Device
Patent:
8,041,759 →
Application:
11/447,370 →
Specialized Processing Block for Programmable Logic Device
Specialized Processing Block for Programmable Logic Device
Patent:
8,301,681 →
Application:
11/447,474 →
Field Programmable Gate Array Architectures and Methods for Supporting Forward Error Correction
Patent:
7,869,343 →
Application:
11/447,745 →
System for Improving Memory Interface Data Integrity in Plds
Enhanced Data Converters Using Compression and Decompression
Patent:
7,292,164 →
Application:
11/462,687 →
Techniques for Providing Adjustable on-Chip Termination Impedance
Patent:
7,417,452 →
Application:
11/462,702 →
Apparatus and Methods for Multi-Gate Silicon-on-Insulator Transistors
Configurable Circuits, Ic's, and Systems
Highly Configurable Pll Architecture for Programmable Logic
Embedded Memory Data Transformation Circuitry
Patent:
8,392,674 →
Application:
11/490,747 →
Power-Aware Ram Processing
Patent:
7,877,555 →
Application:
11/510,018 →
Security Ram Block
Patent:
7,752,407 →
Application:
11/517,689 →
Adapter Allowing Unaligned Access to Memory
Patent:
8,219,785 →
Application:
11/527,201 →
Memory Interface Phase-Shift Circuitry to Support Multiple Frequency Ranges
Patent:
8,188,781 →
Application:
11/531,263 →
Vpa Interconnect Circuit
Patent:
7,564,260 →
Application:
11/535,053 →
Configurable Logic Circuits with Commutative Properties
Apparatus and Methods for Adjusting Performance of Integrated Circuits
Efficient Delay Elements
Patent:
7,629,825 →
Application:
11/549,427 →
Enhanced Data Converters Using Compression and Decompression
Patent:
7,394,410 →
Application:
11/560,574 →
Method and System for Improving Memory Interface Data Integrity
Patent:
7,352,299 →
Application:
11/560,673 →
Configurable Circuits, Ic's, and Systems
Vpa Logic Circuits
Generating Cores Using Secure Scripts
Patent:
7,574,679 →
Application:
11/600,982 →
Omnibus Logic Element
Patent:
7,538,579 →
Application:
11/607,171 →
Non-Sequentially Configurable Ic
Configurable Circuits, Ic's and Systems
Power Supply Filtering for Programmable Logic Device Having Heterogeneous Serial Interface Architecture
Patent:
7,903,679 →
Application:
11/622,396 →
Clock Signal Circuitry for Multi-Protocol High-Speed Serial Interface Circuitry
Patent:
7,310,399 →
Application:
11/650,163 →
Next Generation 8B10B Architecture
Programmable Logic Device with on-Chip Nonvolatile User Memory
Patent:
7,550,994 →
Application:
11/668,325 →
Fractional Delay-Locked Loops
Patent:
7,675,332 →
Application:
11/669,845 →
Multiple Data Rate Memory Interface Architecture
Patent:
7,504,855 →
Application:
11/672,438 →
Programmable Logic Device Having Logic Array Block Interconnect Lines That Can Interconnect Logic Elements in Different Logic Blocks
Double exposure photolithographic process
Application:
11/710,650 →
Publication:
US 2007/0243492
Memory array circuitry with stability enhancement features
Application:
11/711,969 →
Soft Error Location and Sensitivity Detection for Programmable Devices
Megafunction Block and Interface
Patent:
7,724,598 →
Application:
11/737,654 →
Programmable Logic Device Having Redundancy with Logic Element Granularity
Method and Apparatus for Accessing Contents of Memory Cells
Method and System for Using Boundary Scan in a Programmable Logic Device
Patent:
7,550,995 →
Application:
11/768,880 →
Leakage Compensation and Improved Setup/Hold Time in a Dynamic Flip-Flop
Patent:
7,893,726 →
Application:
11/782,443 →
H-Tree Driver Circuitry
Patent:
7,514,968 →
Application:
11/786,295 →
Low-Power Transceiver Architectures for Programmable Logic Integrated Circuit Devices
Patent:
7,403,035 →
Application:
11/788,561 →
High-Performance Memory Interface Circuit Architecture
Patent:
7,535,275 →
Application:
11/789,598 →
Write-Leveling Implementation in Programmable Logic Devices
Method and Apparatus for Reduced Power Cell
Variable Current Charge Pump with Modular Switch Circuit
Patent:
7,570,105 →
Application:
11/867,416 →
High-Speed Charge Pump Circuits
Patent:
7,977,984 →
Application:
11/871,994 →
Configurable Clock Network for Programmable Logic Device
Patent:
7,646,237 →
Application:
11/888,336 →
Flexible High-Speed Serial Interface Architectures for Programmable Integrated Circuit Devices
Patent:
7,602,212 →
Application:
11/904,003 →
Apparatus and Methods for Multi-Gate Silicon-on-Insulator Transistors
Pvt Compensated Auto-Calibration Scheme for DDR3
Patent:
7,590,008 →
Application:
11/936,036 →
Adjustable Transistor Body Bias Generation Circuitry with Latch-Up Prevention
Integrated Circuit Architectures with Heterogeneous High-Speed Serial Interface Circuitry
Patent:
7,759,972 →
Application:
11/981,934 →
Serializer-Deserializer Circuits Formed from Input-Output Circuit Registers
Patent:
7,587,537 →
Application:
11/998,603 →
Via Programmable Gate Array with Offset Direct Connections
Method of Reducing Leakage Current Using Sleep Transistors in Programmable Logic Device
Patent:
7,518,399 →
Application:
12/030,083 →
Enhanced Data Converters Using Compression and Decompression on a Single Integrated Circuit
Patent:
7,649,484 →
Application:
12/040,437 →
Omnibus Logic Element
Patent:
7,671,625 →
Application:
12/043,087 →
Latch-Up Prevention Circuitry for Integrated Circuits with Transistor Body Biasing
Normalization of Floating Point Operations in a Programmable Integrated Circuit Device
Patent:
8,244,789 →
Application:
12/048,379 →
Configurable Ic with Packet Switch Network
Apparatus and Methods for Adjusting Performance of Programmable Logic Devices
Application:
12/054,382 →
Publication:
US 2008/0164936
Techniques for Testing Memory Circuits
Patent:
7,761,754 →
Application:
12/055,099 →
Stacked Die Network-on-Chip for Fpga
Patent:
7,701,252 →
Application:
12/074,467 →
Techniques for Measuring Voltages in a Circuit
Runtime Loading of Configuration Data in a Configurable Ic
Techniques for Level Shifting Signals
Patent:
8,030,964 →
Application:
12/121,028 →
Charge Pump with Reduced Current Mismatch
Patent:
7,902,888 →
Application:
12/121,740 →
Static Random-Access Memory with Boosted Voltages
Phase-Locked Loop Circuitry with Multiple Voltage-Controlled Oscillators
Flexible Ram Clock Enable
Techniques for Providing Adjustable on-Chip Termination Impedance
Patent:
7,825,682 →
Application:
12/147,403 →
Ball Grid Array Package-to-Board Interconnect Co-Design Apparatus
Patent:
7,514,789 →
Application:
12/147,411 →
Distributed Memory in Field-Programmable Gate Array Integrated Circuit Devices
Dynamically-Adjustable Differential Output Drivers
Patent:
7,675,326 →
Application:
12/163,709 →
Digitally Controlled Oscillators
Apparatus and Methods for Power Management in Integrated Circuits
Debuggable Opaque Ip
Patent:
9,064,068 →
Application:
12/168,697 →
Volatile Memory Elements with Elevated Power Supply Levels for Programmable Logic Device Integrated Circuits
Using Dedicated Read Output Path to Reduce Unregistered Read Access Time for a Fpga Embedded Memory
Patent:
7,715,271 →
Application:
12/176,592 →
Memory with Addressable Subword Support
Patent:
7,916,572 →
Application:
12/181,311 →
Method of Mapping a User Design Defined for a User Design Cycle to an Ic with Multiple Sub-Cycle Reconfigurable Circuits
Efficient Delay Elements
Data Encoding Scheme to Reduce Sense Current
Patent:
7,978,493 →
Application:
12/212,801 →
Low-Power Transceiver Architectures for Programmable Logic Integrated Circuit Devices
Debug Network for a Configurable Ic
Techniques for Generating Pvt Compensated Phase Offset to Improve Accuracy of a Locked Loop
Patent:
8,237,475 →
Application:
12/248,031 →
Integrated Circuits with Fuse Programming and Sensing Circuitry
Patent:
8,154,942 →
Application:
12/272,727 →
Bit Slip Circuitry for Serial Data Signals
Patent:
8,477,897 →
Application:
12/283,617 →
Saturation and Rounding in Multiply-Accumulate Blocks
Application:
12/324,055 →
Publication:
US 2009/0100122
Memory Elements with Body Bias Control
Patent:
8,081,502 →
Application:
12/345,560 →
Multiple Data Rate Memory Interface Architecture
Patent:
7,994,816 →
Application:
12/368,308 →
Memory Elements with Increased Write Margin and Soft Error Upset Immunity
Patent:
7,920,410 →
Application:
12/391,230 →
Programmable Logic Device with Differential Communications Support
Patent:
7,958,416 →
Application:
12/393,018 →
Volatile Memory Elements with Minimized Area and Leakage Current
Patent:
8,081,503 →
Application:
12/395,598 →
Omnibus Logic Element for Packing or Fracturing
Patent:
7,911,230 →
Application:
12/425,342 →
Area-Efficient Memory Built-in-Self-Test Circuitry with Advanced Debug Capabilities for Distributed Memory Blocks
Patent:
8,004,915 →
Application:
12/463,358 →
High-Performance Memory Interface Circuit Architecture
Patent:
7,969,215 →
Application:
12/467,681 →
Methods and systems for reducing interrupt latency by using a dedicated bit
Patent:
8,135,894 →
Application:
12/533,980 →
Charge Pump with Ramp Rate Control
Patent:
8,120,411 →
Application:
12/534,007 →
Apparatus and Methods for Adjusting Performance of Integrated Circuits
Mems Switching Device and Conductive Bridge Device Based Circuits
Patent:
8,130,559 →
Application:
12/535,395 →
Pvt Compensated Auto-Calibration Scheme for DDR3
Patent:
7,983,094 →
Application:
12/539,594 →
Techniques for Providing Multiple Delay Paths in a Delay Circuit
Patent:
7,893,739 →
Application:
12/549,332 →
Memory Element Circuitry with Stressed Transistors
Patent:
8,218,353 →
Application:
12/561,236 →
Memory Elements with Soft Error Upset Immunity
Patent:
8,797,790 →
Application:
12/568,638 →
Volatile Memory Elements with Soft Error Upset Immunity
Patent:
8,289,755 →
Application:
12/571,346 →
Heterogeneous Transceiver Architecture for Wide Range Programmability of Programmable Logic Devices
Configurable Allocation of Thread Queue Resources in an Fpga
Patent:
8,166,237 →
Application:
12/605,222 →
Compression of Sampled Data in a Data Acquisition System
Patent:
7,876,252 →
Application:
12/609,973 →
Techniques for Configuring Multi-Path Feedback Loops
Patent:
8,125,254 →
Application:
12/613,465 →
Configurable Clock Network for Programmable Logic Device
Patent:
7,859,329 →
Application:
12/625,718 →
Integrated Circuits with Asymmetric and Stacked Transistors
Patent:
8,482,963 →
Application:
12/629,831 →
Techniques for Providing Reduced Duty Cycle Distortion
Non-Sequentially Configurable Ic
Fractional Delay-Locked Loops
Patent:
7,940,098 →
Application:
12/701,346 →
User Registers Implemented with Routing Circuits in a Configurable Ic
Stacked Die Network-on-Chip for Fpga
Patent:
8,719,753 →
Application:
12/703,681 →
Phase-Locked Loop Architecture and Clock Distribution System
Patent:
8,228,102 →
Application:
12/717,062 →
Integrated Circuit Guard Ring Structures
Patent:
8,492,873 →
Application:
12/717,796 →
Techniques for on-Chip Termination
Patent:
7,973,553 →
Application:
12/721,759 →
Configuration Network for an Ic
Runtime Loading of Configuration Data in a Configurable Ic
Voltage Regulator with High Noise Rejection
Patent:
8,237,425 →
Application:
12/760,643 →
Stacked Die Network-on-Chip for Fpga
Patent:
8,863,065 →
Application:
12/775,363 →
Voltage-Controlled Oscillator Methods and Apparatus
Patent:
8,120,429 →
Application:
12/787,722 →
Level Shifter Circuit with a Thin Gate Oxide Transistor
Patent:
8,049,532 →
Application:
12/823,596 →
Methods and Systems for Managing a Write Operation
Patent:
8,242,806 →
Application:
12/829,206 →
Security Ram Block
Application:
12/830,447 →
Techniques for Testing Memory Circuits
Patent:
7,984,344 →
Application:
12/839,319 →
Methods and Systems for Measuring and Presenting Performance Data of a Memory Controller System
Patent:
8,499,201 →
Application:
12/841,762 →
Segmented Clock Network for Transceiver Array
Patent:
8,612,795 →
Application:
12/847,268 →
Memory Array Circuitry with Stability Enhancement Features
Patent:
8,705,300 →
Application:
12/850,528 →
Configurable Memory Block
Patent:
8,400,863 →
Application:
12/860,734 →
Accessing Multiple User States Concurrently in a Configurable Ic
Memory Elements with Voltage Overstress Protection
Patent:
8,369,175 →
Application:
12/874,152 →
System and Method for Providing More Logical Memory Ports Than Physical Memory Ports
Booting Mechanism for Fpga-Based Embedded System
Patent:
8,412,918 →
Application:
12/887,982 →
SDRAM Memory Organization and Efficient Access
Patent:
9,424,210 →
Application:
12/910,423 →
Memory Array with Redundant Bits and Memory Element Voting Circuits
Configurable Clock Network for Programmable Logic Device
Patent:
8,072,260 →
Application:
12/951,486 →
Configurable Circuits, Ic's, and Systems
Memory Array with Distributed Clear Transistors and Variable Memory Element Power Supply
Patent:
8,411,491 →
Application:
12/983,816 →
Power-Aware Ram Processing
Patent:
9,330,733 →
Application:
13/012,717 →
Trigger Circuits and Event Counters for an Ic
Charge Pump with Reduced Current Mismatch
Techniques for Providing Multiple Delay Paths in a Delay Circuit
Patent:
8,159,277 →
Application:
13/031,129 →
Delay Circuitry
Power Supply Filtering for Programmable Logic Device Having Heterogeneous Serial Interface Architecture
Patent:
8,976,804 →
Application:
13/041,764 →
Omnibus Logic Element for Packing or Fracturing
Patent:
8,237,465 →
Application:
13/050,732 →
Memory Elements with Increased Write Margin and Soft Error Upset Immunity
Patent:
8,711,614 →
Application:
13/052,374 →
Trigger Circuits and Event Counters for an Ic
Non-Sequentially Configurable Ic
Setting Security Features of Programmable Logic Devices
Patent:
8,736,299 →
Application:
13/098,316 →
Apparatus and Methods for Adjusting Performance of Programmable Logic Devices
Static Random-Access Memory with Boosted Voltages
Heterogeneous Transceiver Architecture for Wide Range Programmability of Programmable Logic Devices
Techniques for Measuring Voltages in a Circuit
Integrated Circuits with Asymmetric Transistors
Patent:
8,638,594 →
Application:
13/110,823 →
Programmable Logic Device with Differential Communications Support
Patent:
8,086,922 →
Application:
13/113,809 →
Multiport Memory Element Circuitry
Methods for Calibrating Memory Interface Circuitry
Patent:
8,565,033 →
Application:
13/149,562 →
Memory Controllers with Dynamic Port Priority Assignment Capabilities
Memory Controller Interface with Adjustable Port Widths
Patent:
9,244,867 →
Application:
13/151,123 →
Data Encoding Scheme to Reduce Sense Current
Integrated Circuit Inductors with Intertwined Conductors
Saturation and Rounding in Multiply-Accumulate Blocks
Patent:
8,615,543 →
Application:
13/166,119 →
Memory Elements with a Configurable Number of Ports
Patent:
8,514,613 →
Application:
13/167,496 →
High-Performance Memory Interface Circuit Architecture
Patent:
8,305,121 →
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Multiple Data Rate Memory Interface Architecture
Method and System for Operating a Multi-Port Memory System
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Area-Efficient Memory Built-in-Self-Test Circuitry with Advanced Debug Capabilities for Distributed Memory Blocks
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Memory Elements with Elevated Control Signal Levels for Integrated Circuits
Systems and Methods for Providing Memory Controllers with Memory Access Request Merging Capabilities
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Digitally Controlled Oscillators
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First-In-First-Out Memory with Dual Memory Banks
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Runtime Loading of Configuration Data in a Configurable Ic
Configurable Clock Network for Programmable Logic Device
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3T Device Based Memory Circuits and Arrays
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Systems and Methods for Stacking a Memory Chip Above an Integrated Circuit Chip
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Logic Block Protection System
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Memory Elements with Relay Devices
Fast Parallel-to-Serial Memory Data Transfer System and Method
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Logic Device Having a Compressed Configuration Image Stored on an Internal Read Only Memory
User Registers Implemented with Routing Circuits in a Configurable Ic
Temperature Dependent Power Supply Circuitry
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Apparatus for Improving Power Consumption of Communication Circuitry and Associated Methods
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Write-Leveling Implementation in Programmable Logic Devices
Memory Circuit with PMOS Access Transistors
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Hierarchical Arbitration
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Transition Accelerator Circuitry
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Memory Circuitry with Dynamic Power Control
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Integrated Circuits with Multi-Stage Logic Regions
Memory Interface Phase-Shift Circuitry to Support Multiple Frequency Ranges
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Techniques for Measuring Voltages in a Circuit
Configurable Circuits, Ic's, and Systems
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Digital Pvt Compensation for Delay Chain
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Methods and Systems for Axi Id Compression
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Phase-Locked Loop Architecture and Clock Distribution System
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Omnibus Logic Element for Packing or Fracturing
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Normalization of Floating Point Operations in a Programmable Integrated Circuit Device
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Configurable Clock Network for Programmable Logic Device
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High Performance Memory Interface Circuit Architecture
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Non-Sequentially Configurable Ic
Circuitry for Generating Peak Cancelling Pulses
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Trigger Circuits and Event Counters for an Ic
Multi-Chip Packages with Reduced Power Distribution Network Noise
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Methods and Apparatus for Memory Interface Systems
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Memory Interface Circuitry with Improved Timing Margins
Memory Interface Circuitry with Data Strobe Signal Sharing Capabilities
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Delaying Start of User Design Execution
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System and Methods for Adjusting Memory Command Placement
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Methods and Apparatus for Performing Boosted Bit Line Precharge
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Circuits and Methods for Dqs Autogating
Transceiver Circuitry with Multiple Phase-Locked Loops
Patent:
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Variable Gate Width Finfet
Patent:
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Methods and Apparatus for Performing Runtime Data Eye Monitoring and Continuous Data Strobe Calibration
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Circuitry and Techniques for Image Processing
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Configurable Clock Network for Programmable Logic Device
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Bit Slip Circuitry for Serial Data Signals
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Integrated Circuits with Asymmetric and Stacked Transistors
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Method for Reconfiguring an Erroneous Memory Frame in an Integrated Circuit
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Multiple Data Rate Memory Interface Architecture
Supporting Pseudo Open Drain Input/Output Standards in a Programmable Logic Device
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Integrated Circuit Package with Vacant Cavity
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Phase-Locked Loop Architecture and Clock Distribution System
Patent:
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Address Arithmetic on Block Rams
Patent:
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Omnibus Logic Element
Patent:
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Methods and Circuitry for Identifying Logic Regions Affected by Soft Errors
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Memory Circuit Including Memory Devices, a Freeze Circuit and a Test Switch
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Configurable Storage Circuits with Embedded Processing and Control Circuitry
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Memory Elements with Relay Devices
First-in First-out Circuits and Methods
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Integrated Circuits with Asymmetric Transistors
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Via Structure and Method for Its Fabrication
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Configuration Bit Architecture for Programmable Integrated Circuit Device
Configurable Clock Network for Programmable Logic Device
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Methods for Packaging Integrated Circuits
User Registers Implemented with Routing Circuits in a Configurable Ic
Fused Floating Point Datapath with Correct Rounding
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Digital Pvt Compensation for Delay Chain
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Configurable Storage Blocks with Embedded First-in First-Out and Last-in First-Out Circuitry
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Memory Elements With Soft Error Upset Immunity
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Method and Apparatus for Power Supply Aware Memory Access Operations in an Integrated Circuit
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Setting Security Features of Programmable Logic Devices
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Lc Tank Circuitry with Shielding Structures
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Application:
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Runtime Loading of Configuration Data in a Configurable Ic
Integrated Circuits with Asymmetric and Stacked Transistors
Memory Array with Redundant Bits and Memory Element Voting Circuits
Trigger Circuits and Event Counters for an IC
Apparatus and Methods for Power Management in Integrated Circuits
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US 2014/0258956
Multiport Memory Element Circuitry
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Bit Slip Circuitry for Serial Data Signals
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Non-Sequentially Configurable IC
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Publication:
US 2015/0130508
Programmable Integrated Circuits with in-Operation Reconfiguration Capability
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Content Addressable Memory in Integrated Circuit
Circuits and Methods For Impedance Calibration
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Integrated Circuits Having Input-Output Circuits with Dedicated Memory Controller Circuitry
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Phase-Locked Loop Architecture and Clock Distribution System
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Omnibus Logic Element
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Embedded Interposer with Through-Hole Vias
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Integrated Circuit Voltage Regulator with Adaptive Current Bleeder Circuit
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Electrostatic Discharge Circuitry with Separate Power Rails
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Application:
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Memory Cells with P-Type Diffusion Read-Only Port
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Apparatus and Method for Sense Amplifier Offset Cancellation
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Runtime Loading of Configuration Data in a Configurable Ic
User Registers Implemented with Routing Circuits in a Configurable Ic
Memory Element Write-Assist Circuitry with Dummy Bit Lines
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Security Ram Block with Multiple Partitions
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Publication:
US 2016/0248588
Integrated Circuits with Embedded Double-Clocked Components
Integrated Circuits with Guard Ring Structures for Nonplanar Transistor Devices
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State Visibility and Manipulation in Integrated Circuits
Methods for Initializing Memory Devices
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Delaying Start of User Design Execution
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Integrated Circuit with Overdriven and Underdriven Pass Gates
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Circuits and Methods for Dqs Autogating
Programmable Integrated Circuits with in-Operation Reconfiguration Capability
Patent:
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Fused Floating Point Datapath with Correct Rounding
Patent:
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Application:
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Phase-Locked Loop Architecture and Clock Distribution System
Patent:
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Memory Elements with Dynamic Pull-Up Weakening Write Assist Circuitry
Patent:
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Circuits and Methods For Impedance Calibration
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Application:
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Emulated Multiport Memory Element Circuitry with Exclusive-or Based Control Circuitry
Address Arithmetic on Block Rams
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Application:
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Phase-Locked Loops with Electrical Overstress Protection Circuitry
Methods for Packaging Integrated Circuits
Methods and Apparatus for Smart Memory Interface
Lutram Dummy Read Scheme During Error Detection and Correction
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Apparatus For Improving Power Consumption Of Communication Circuitry And Associated Methods
Memory Interface Circuitry with Distributed Data Reordering Capabilities
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Circuitry for Reducing Leakage Current in Configuration Memory
Systems and Methods for Refreshing Data in Memory Circuits
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Omnibus Logic Element
Patent:
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Application:
15/351,167 →
Variable Gate Width Finfet
Patent:
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Application:
15/356,278 →
Security Ram Block with Multiple Partitions
Patent:
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Programmable Integrated Circuits with in-Operation Reconfiguration Capability
Circuits and Methods For Impedance Calibration
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Publication:
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State Visibility and Manipulation in Integrated Circuits
Circuits and Methods for Dqs Autogating
Application:
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Publication:
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Supporting Pseudo Open Drain Input/Output Standards in a Programmable Logic Device
Setting Security Features of Programmable Logic Devices
Memory Interface Circuitry with Distributed Data Reordering Capabilities
Configurable integrated circuits with programmable vias
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60/560,747 →
Configuration and debug network for configurable ICs
Application:
60/699,463 →
Power-aware RAM processing
Application:
60/719,251 →
Method to provide floating point arithmetic functions for FPGA
Application:
60/771,988 →
Method to implement rounding and saturation function for DSP applications in FPGA
Application:
60/771,989 →
Flexible hardwired DSP block for FPGA devices
Application:
60/772,197 →
Method to perform filtering and other DSP functions in FPGA
Application:
60/772,465 →
Techniques for sensing temperature and automatic calibration on integrated circuits
Application:
60/786,129 →
Specialized processing block for program mable logic device
Application:
60/789,535 →
Techniques for providing flexible on-chip termination control on integrated circuits
Application:
60/789,760 →
Double exposure photo lithographic process
Application:
60/792,038 →
Soft error location and sensitivity detection for PLDs
Application:
60/793,946 →
Write-leveling implementation in programmable logic devices
Application:
60/840,107 →
PVT compensated dynamic auto-calibration scheme for simplifying high performance DDR3 memory interface design in FPGAs
Application:
60/857,467 →
Stacked die network-on chip for FPGA
Application:
61/002,162 →
GUI for Tracking Data Values in an IC
Application:
61/086,145 →
Memory Elements with Soft Error Upset Immunity for Integrated Circuits
Application:
61/102,000 →
Memory Elements with Controllable Inverter Circuitry
Application:
61/102,003 →
Volatile Memory Elements with Soft Error Upset Immunity
Application:
61/113,573 →
Memory Elements with Soft Error Upset Immunity
Application:
61/120,334 →
Cantilever device and 3T device based memory circuits and multiplexers
Application:
61/188,081 →
Advanced eXtensible Interface (AXI) ID Compression Scheme
Application:
61/539,602 →
High-Speed, Low-Area Arbitration
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61/544,951 →
Content Addressable Memory in an Integrated Circuit
Application:
61/558,984 →
Delayed Start of User Design
Application:
61/576,972 →
Integrated Circuits Having Input-Output Circuits with Dedicated Memory Controller Circuitry
Application:
61/873,268 →
Area Efficient and Highspeed Esd Protection Scheme
Application:
61/925,796 →
Memory Element Write-Assist Circuitry with Dummy Bit Lines
Application:
62/091,423 →
Method to Initialize a Memory Device
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62/101,842 →
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Nov 1, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061827/0686 →
Release of Security Interest
Feb 29, 2024
From: MONROE CAPITAL MANAGEMENT ADVISORS, LLC, AS AGENT
To: EXIGER CANADA, INC.
Reel/Frame 066605/0809 →
Release of Security Interest
Feb 29, 2024
From: MONROE CAPITAL MANAGEMENT ADVISORS, LLC, AS AGENT
To: EXIGER CANADA, INC.
Reel/Frame 066605/0930 →