Phase-locked loop architecture and clock distribution system
View Patent ↗One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.
1. A fracture-able phase-locked loop circuit comprising:
a first phase-locked loop circuit that generates a first frequency output;
a second phase-locked loop circuit that generates a second frequency output;
a plurality of counter circuits that receive the first and second frequency outputs from the first and second phase-locked loop circuits, respectively, and that generate output signals;
physical media attachment circuitry that receives the first and second frequency outputs from the first and second phase-locked loop circuits, respectively, and receives the output signals from the plurality of counter circuits; and
clock input circuitry including first and second input multiplexers and clock-lost-detect and switch-over circuitry,
wherein the first and second input multiplexers each receives a plurality of clock signals and selects an output clock signal from the plurality of clock signals, and
wherein the clock-lost-detect and switch-over circuitry.
2. The fracture-able phase-locked loop circuit of claim 1 , further comprising:
a shared power source for the first and second phase-locked loop circuits, wherein the shared power source comprises a power distribution network that receives power from a plurality of power input contacts, wherein each power input contact receives power via one ball or pin of an integrated circuit package.
3. The fracture-able phase-locked loop circuit of claim 1 , wherein the plurality of counters include at least fourteen shared output counters.
4. The fracture-able phase-locked loop circuit of claim 1 , further comprising:
low-voltage differential signal system circuitry that receives the first and second frequency outputs from the first and second phase-locked loop circuits, respectively, and receives the output signals from the plurality of counter circuits.
5. The fracture-able phase-locked loop circuit of claim 1 , further comprising:
dynamic phase aligners that receives the first and second frequency outputs from the first and second phase-locked loop circuits, respectively, and receives the output signals from the plurality of counter circuits.
6. The fracture-able phase-locked loop circuit of claim 1 , further comprising:
memory interface system circuitry that receives the output signals from the plurality of counter circuits.
7. The fracture-able phase-locked loop circuit of claim 1 , further comprising:
circuitry to allow each phase-locked loop circuit to be configured into either an integer phase-locked loop or a fractional phase-locked loop.
8. A method of providing clock signals for multiple purposes in an integrated circuit, the method comprising:
generating a plurality of clock signals by a plurality of multiple-purpose phase-locked loop (PLL) circuits;
selectively distributing the clock signals output by the multiple-purpose PLL circuits to physical media attachment (PMA) modules arranged at a side of the integrated circuit and to logic circuitry arranged in a core section of the integrated circuit; and
using the clock signals by circuitry in the PMA modules for supporting a plurality of data communications channels,
wherein each PMA module of the PMA modules is a PMA triplet module having exactly three clock-data recovery circuits to support three serial data channels.
9. The method of claim 8 , wherein each PMA module of the PMA modules has an adjacent multiple-purpose PLL circuit.
10. The method of claim 8 , wherein use by a PMA module of a clock signal output by a multiple-purpose PLL circuit allows the PMA module to support an additional independent data communication channel.
11. The method of claim 10 , wherein the multiple-purpose PLL circuits include a voltage-controlled oscillator with an operating frequency sufficiently high to support a 3.75 Gbps data rate.