Leakage compensation and improved setup/hold time in a dynamic flip-flop
View Patent ↗A dynamic flip-flop includes first and second input stages forming a differential input stage adapted to receive differential data. The flip-flop is reset in response to a reset signal. To ensure proper operation, a transistor disposed between the first and second input stages is always maintained active to provide a conduction path between the ground terminal and the nodes that may be charged from the supply voltage. To improve the setup and hold time of the flip-flop, the clock signal is applied to a first transistor disposed in the first input stage and a second transistor disposed in the second input stage.
1. A circuit comprising:
a first transistor responsive to a data signal, said first transistor having a first current carrying terminal coupled to a first node;
a second transistor responsive to an inverse of the data signal, said second transistor having a first current carrying terminal coupled to the first node;
a third transistor coupled to the first transistor and a fifth transistor and having a gate terminal responsive to a clock signal;
a fourth transistor coupled to the second transistor and a seventh transistor and having a gate terminal responsive to the clock signal;
sixth, and eight transistors, wherein a gate terminal of each of the fifth and sixth transistors is responsive to an output signal of the seventh and eight transistors, and wherein a gate terminal of each of the seventh and eight transistors is responsive to an output signal of the fifth and sixth transistors, wherein said third transistor has a first current-carrying terminal coupled to a first current-carrying terminal of the fifth transistor and a second current-carrying terminal coupled to a second current carrying terminal of the first transistor, and wherein said fourth transistor has a first current-carrying terminal coupled to a first current-carrying terminal of the seventh transistor and a second current-carrying terminal coupled to a second current carrying terminal of the second transistor;
a ninth transistor having a gate terminal responsive to the clock signal, a first current carrying terminal coupled to the gate terminals of the fifth and sixth transistors, and a second current carrying terminal coupled to the gate terminals of the seventh and eight transistors; and
a tenth transistor having a gate terminal coupled to a first supply voltage, a first current carrying terminal coupled to the second current carrying terminal of the first transistor, and a second current carrying terminal coupled to the second current carrying terminal of the second transistor, said tenth transistor being adapted to conduct current at all times; wherein said first node is not discharged in response to the clock signal.
2. The circuit of claim 1 further comprising:
an eleventh transistor adapted to discharge the first node in response to a reset signal.
3. The circuit of claim 2 further comprising:
a twelfth transistor adapted to charge the gate terminals of the seventh and eight transistors to the second supply voltage in response to the reset signal; and
a thirteenth transistor adapted to charge the gate terminals of the fifth and sixth transistors to the second supply voltage in response to the reset signal.
4. The circuit of claim 3 further comprising:
a fourteenth transistor adapted to charge the gate terminals of the seventh and eight transistors to the second supply voltage in response to the clock signal; and
a fifteenth transistor adapted to charge the gate terminals of the fifth and sixth transistors to the second supply voltage in response to the clock signal.