Multiple data rate memory interface architecture
View Patent ↗The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.
1. An integrated circuit comprising:
a delay circuit;
a group of at least two registers; and
a selection device coupled to the delay circuit, wherein the selection device has an output coupled to the group of registers and wherein lengths of signal paths from the output of the selection device to the at least two registers in the group of registers are about equal.
2. The integrated circuit of claim 1 , further comprising another delay circuit, wherein the selection device is configurable to provide a signal from a selectable one of the delay circuit and the other delay circuit to the group of registers.
3. The integrated circuit of claim 1 , further comprising at least one other group of registers, wherein the selection device is configurable to provide a signal from the delay circuit to a selectable group from the group of registers and the at least one other group of registers.
4. The integrated circuit of claim 1 , further comprising at least one other group of registers, wherein the selection device is configurable to provide a signal from the delay circuit to a selectable portion of the group of registers and the at least one other group of registers.
5. The integrated circuit of claim 1 , wherein the delay circuit is coupled to at least one register from the group of registers through an interconnect having a balanced tree structure.
6. The integrated circuit of claim 5 , wherein the delay circuit is connected to at least two groups of registers each having a midpoint, and wherein the balanced tree structure is configured to provide signal paths with approximately equal lengths from the delay circuit to the midpoints of the at least two groups of registers.
7. The integrated circuit of claim 1 , wherein the selection device comprises a multiplexer configurable by setting at least one configuration bit in the integrated circuit.
8. A method of configuring a programmable integrated circuit device comprising a delay circuit and a group of at least two registers, the method comprising:
configuring logic of said programmable integrated circuit device as a selection device coupled to the delay circuit, wherein the selection device has an output coupled to the group of registers and wherein lengths of signal paths from the output of the selection device to the at least two registers in the group of registers are about equal.
9. The method of claim 8 , wherein the programmable integrated circuit device further comprises another delay circuit, said method further comprising configuring the selection device to provide a signal from a selectable one of the delay circuit and the other delay circuit to the group of registers.
10. The method of claim 8 , wherein the programmable integrated circuit device further comprises at least one other group of registers, said method further comprising configuring the selection device to provide a signal from the delay circuit to a selectable group from the group of registers and the at least one other group of registers.
11. The method of claim 8 , wherein the programmable integrated circuit device further comprises at least one other group of registers, said method further comprising configuring the selection device to provide a signal from the delay circuit to a selectable portion of the group of registers and the at least one other group of registers.
12. The method of claim 8 further comprising coupling the delay circuit to at least one register from the group of registers through an interconnect having a balanced tree structure.
13. The method of claim 12 further comprising:
coupling the delay circuit to at least two groups of registers each having a midpoint; and
configuring the balanced tree structure to provide signal paths with approximately equal lengths from the delay circuit to the midpoints of the at least two groups of registers.
14. The method of claim 8 , wherein the selection device comprises a multiplexer, said method further comprising configuring the multiplexer by setting at least one configuration bit in the programmable integrated circuit device.
15. An integrated circuit comprising:
a plurality of groups of register blocks;
a delay circuit; and
a selection device, wherein:
in response to an input of the selection devices being selected, a set of the groups of register blocks is driven by the delay circuit; and
in response to another input of the selection devices being selected, another set of the groups of register blocks is driven by the delay circuit.
16. The integrated circuit of claim 15 , wherein:
in response to the input of the selection device being selected, at least one of the groups of register blocks is driven by the delay circuit; and
in response to the other input of the selection device being selected, one pair of the groups of register blocks is driven by the delay circuit.
17. The integrated circuit of claim 15 , wherein:
in response to the input of the selection device being selected, the set of the groups of register blocks is driven by the delay circuit through a path comprising at least a first number of buffers; and
in response to the other input of the selection device being selected, the other set of the groups of register blocks is driven by the delay circuit through a path comprising at least a second number of buffers, wherein the first number is different from the second number.
18. The integrated circuit of claim 17 , wherein at least one of the buffers comprises an inverter.
19. The integrated circuit of claim 15 , wherein the selection device comprises a multiplexer that is programmable using a configuration bit.
20. The integrated circuit of claim 15 , wherein at least one register block comprises a double-data-rate register.