Debuggable opaque IP
View Patent ↗Partially opaque intellectual property (IP) includes source code providing the IP functionality. Meta-comments (pragmas or attributes) are provided with the source code to enable visibility of one or more nodes in the IP. Aliasing of the visibility-enabled nodes may also be provided for using meta-comments in the IP source code. The visibility-enabled nodes may be used by system designers in debugging a system design in either a software simulation environment and/or in debugging of a hardware device implementing the partially opaque IP.
1. A programmable logic development system arranged to debug an electronic circuit design, the system comprising:
a hardware device including
a hardware representation of the electronic circuit design implemented thereon,
an opaque logic block included within said electronic circuit design having one or more internal nodes not normally being visible to a user debugging the electronic circuit design, and
at least one visibility attribute of said opaque logic block designating said one or more internal nodes;
a node locating software tool arranged to understand said at least one visibility attribute and to display said one or more internal nodes to said user, whereby said one or more nodes are made visible to said user;
a computer having software arranged to deliver control signals to the hardware device and to collect response signals from the hardware device to assist in debugging the electronic circuit design; and
a communication medium in electrical communication with the computer and the hardware device, said communication medium being arranged to deliver the control signals to the hardware device from said computer and to deliver the response signals to the computer from said hardware device.
2. The system of claim 1 wherein the hardware device is a computer running a software simulation of the electronic design.
3. The system of claim 2 wherein the computer running the simulation of the electronic design and the computer having software arranged to deliver control signals and to collect response signals are the same computer.
4. The system of claim 1 wherein the hardware device is a programmable device having the electronic design implemented thereon.
5. The system of claim 1 wherein the opaque logic block is an encrypted logic block.
6. The system of claim 1 wherein the representation of the electronic design further comprises:
at least one alias attribute designating said one or more internal nodes, wherein the opaque logic block is providing aliasing for any visible nodes, whereby a meaningful name is provided for said visible nodes.
7. A programmable logic development system as recited in claim 1 wherein said at least one visibility attribute is implemented as an extra logic cell in said hardware device.