Heterogeneous transceiver architecture for wide range programmability of programmable logic devices
View Patent ↗High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
1. A serial data receiver comprising:
a plurality of channels each having a serial bit rate operating range, wherein each of the plurality of channels is operable to receive a serial data signal and operate at the serial bit rate operating range, and wherein a first serial bit rate operating range of a first channel of the plurality of channels exceeds a second serial bit rate operating range of a second channel of the plurality of channels;
a set of first conductors that distribute a first and a second clock signal, generated respectively by a first and a second phase-locked loop circuitry, to the second channel;
a second conductor that distributes the second clock signal to the first channel, wherein the first clock signal is suitable for a third serial bit rate operating range and the second clock signal is suitable for a fourth serial bit rate operating range, and wherein the fourth serial bit rate operating range exceeds the third serial bit rate operating range; and
circuitry for allowing the second channel to select the first or the second clock signal for use by the second channel.
2. The serial data receiver of claim 1 , wherein the first clock signal is suitable for at least a 6 Gbps serial bit rate operating range and the second clock signal is suitable for at least a 10 Gbps serial bit rate operating range.
3. The serial data receiver of claim 1 , wherein the first channel is operable to receive the second clock signal but not the first clock signal.
4. The serial data receiver of claim 1 further comprising:
a programmable element associated with the second channel, wherein the programmable element is operable to couple the second channel to either (1) one of the first conductors or (2) the second conductor.
5. The serial data receiver of claim 1 , wherein the first serial bit rate operating range of the first channel is 10 Gbps and the second serial bit rate operating range of the second channel is 6 Gbps.
6. The serial data receiver of claim 1 , wherein the first serial bit rate operating range of the first channel is at least 10 Gbps and the second serial bit rate operating range of the second channel is at least 6 Gbps.
7. The serial data receiver of claim 1 , wherein:
a third channel of the plurality of channels is operable to operate at the second serial bit rate operating range;
the set of first conductors distribute the first and a third clock signal to the third channel; and
the circuitry allows the third channel to select the first or the third clock signal for use by the third channel.
8. The serial data receiver of claim 1 , wherein the first serial bit rate operating range is a maximum serial bit rate operating range of the first channel and the second serial bit rate operating range is a maximum serial bit rate operating range of the second channel.
9. The serial data receiver of claim 1 , wherein the first channel includes a first clock data recovery circuit operable to operate at the first bit rate operating range and the second channel includes a different second clock data recovery circuit operable to operate at the second bit rate operating range.
10. A method for configuring a plurality of transceiver channels, the method comprising:
configuring a first channel of the plurality of transceiver channels to receive a serial data signal, wherein a first serial bit rate operating range of the first channel exceeds a second serial bit rate operating range of a second channel of the plurality of transceiver channels;
causing a first and a second clock signal, generated respectively by a first and a second phase-locked loop circuitry, to be distributed to the second channel;
configuring the second clock signal to be coupled to the first channel, wherein the first clock signal is suitable for a third serial bit rate operating range and the second clock signal is suitable for a fourth serial bit rate operating range, and wherein the fourth serial bit rate operating range exceeds the third serial bit rate operating range; and
allowing the second channel to select the first clock signal or the second clock signal for use by the second channel.
11. The method of claim 10 , wherein the first clock signal is suitable for at least a 6 Gbps serial bit rate operating range and the second clock signal is suitable for at least a 10 Gbps serial bit rate operating range.
12. The method of claim 10 , wherein the first channel is operable to receive the second clock signal but not the first clock signal.
13. The method of claim 10 , wherein the first serial bit rate operating range of the first channel is 10 Gbps and the second serial bit rate operating range of the second channel is 6 Gbps.
14. The method of claim 10 , wherein the first serial bit rate operating range of the first channel is at least 10 Gbps and the second serial bit rate operating range of the second channel is at least 6 Gbps.
15. The method claim 10 , wherein a third channel of the plurality of channels is operable to operate at the second serial bit rate operating range, further comprising:
causing the first and a third clock signal to distributed to the third channel; and
allowing the third channel to select the first or the third clock signal for use by the third channel.
16. The method of claim 10 , wherein the first serial bit rate operating range is a maximum serial bit rate operating range of the first channel and the second serial bit rate operating range is a maximum serial bit rate operating range of the second channel.
17. The method of claim 10 , wherein the first channel includes a first clock data recovery circuit operable to operate at the first bit rate operating range and the second channel includes a different second clock data recovery circuit operable to operate at the second bit rate operating range.
18. The method of claim 10 further comprising configuring the first clock signal and the second clock signal to be selectively supplied to the second channel.