Omnibus logic element for packing or fracturing
View Patent ↗Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
1. An integrated circuit (IC) comprising:
a first logic element (LE) including a first lookup table (LUT); and
a second LE comprising a second LUT, a third LUT, and an adder, wherein
at least one of the first LUT, the second LUT, and the third LUT is configured to perform as a fracturable LUT that is configured to enable a respective LE to implement a first number of input logic functions in a first mode and a second number of input logic functions in a second mode;
the adder (i) receives, when the IC is configured in a ternary addition mode, a first output from the first LUT and a second output from the second LUT, and (ii) receives, when the IC is configured in a binary addition mode, the second output from the second LUT and a third output from the third LUT.
2. The IC of claim 1 , wherein at least one of the first LUT, the second LUT and the third LUT is operable to implement n number of input logic functions in the first mode and two times (n−1) number of input logic functions in the second mode.
3. The IC of claim 1 , wherein each of the first LUT, the second LUT, and the third LUT is configured to perform as a fracturable LUT that is configured to enable a respective LE to implement a first number of input logic functions in a first mode and a second number of input logic functions in a second mode.
4. The IC of claim 3 , further comprising a multiplexer, wherein:
the first LUT, the second LUT, and the third LUT are each configured to enable a respective LE to implement n number of input logic functions in a first mode and two times (n−1) number of input logic functions in a second mode;
the first LUT produces a carry from a first set of corresponding bits of at least three binary numbers;
the second LUT produces a sum from a second set of corresponding bits of the at least three binary numbers;
the adder is coupled with the first LUT and the second LUT, and is configured to add the carry and the sum; and
the multiplexer is coupled with the first LUT and the third LUT, and is configured to select between a signal received from the first LUT and a signal received from the third LUT for forwarding to the adder.
5. A programmable logic device comprising:
a plurality of logic elements arranged in an array, at least one logic element of the plurality of logic elements including (i) a fracturable lookup table (LUT) and (ii) arithmetic logic to perform arithmetic logic functions, wherein the arithmetic logic is configurable to implement a ternary adder; wherein,
the fracturable LUT is configured to enable the at least one logic element to implement a first number of input logic functions in a first mode and a second number of input logic functions in a second mode.
6. The programmable logic device of claim 5 , wherein the fracturable LUT has shared inputs.
7. The programmable logic device of claim 5 , wherein the fracturable LUT is configured to implement n number of input logic functions in the first mode and two times (n−1) number of input logic functions in the second mode.
8. The programmable logic device of claim 5 , wherein the arithmetic logic is configurable to implement a binary adder.
9. The programmable logic device of claim 8 , wherein the at least one logic element is configurable to implement a 4-input LUT function.
10. The programmable logic device of claim 8 , wherein each logic element of the plurality of logic elements is further capable of implementing a 6-input LUT.
11. The programmable logic device of claim 5 , wherein the at least one logic element is configurable to perform register packing of at least a first register and a second register.
12. The programmable logic device of claim 5 , wherein the at least one logic element is configurable to have a shared LUT mask drive a register.
13. The programmable logic device of claim 5 , wherein the at least one logic element is configurable to implement two ternary adders and two packed registers.
14. An integrated circuit (IC) comprising:
a first logic element including a first look up table (LUT), the first LUT being configured to output a carry result from a first set of corresponding bits of at least three binary numbers; and
a second logic element including a second LUT and a third LUT, the second logic element being configured to:
(i) select between a first signal received from the first LUT and a second signal received from the third LUT;
(ii) output a sum result from a second set of corresponding bits of the at least three binary numbers; and
(iii) add the carry result and the sum result; wherein
at least one of the first LUT, the second LUT and the third LUT is configured as a fracturable LUT, operable to implement a first number of input logic functions in a first mode and a second number of input logic functions in a second mode.
15. The IC of claim 14 , wherein at least one of the first LUT, the second LUT and the third LUT is operable to implement n number of input logic functions in the first mode and two times (n−1) number of input logic functions in the second mode.
16. The IC of claim 14 , wherein at least one of the first LUT and the second LUT determines a one bit carry of three binary numbers in a carry save adder process.
17. The IC of claim 14 , wherein at least one of the first LUT and the second LUT receives bits X[n], Y[n], and Z[n] and provides as an output ((X[n] AND Y[n]) OR (X[n] AND Z[n]) OR (Y[n] AND Z[n])), wherein n is an integer, X[n], Y[n], and Z[n] are the n-th bits of binary numbers X, Y, and Z, further wherein OR designates the Boolean OR function, and AND designates the Boolean AND function.
18. The IC of claim 14 , wherein the IC is a programmable logic device.
19. The IC of claim 14 , wherein:
the first logic element (LE) includes a fourth LUT, a fifth LUT, a sixth LUT, a first adder, a second adder, a first multiplexer, having first and second input terminals and a first output terminal, and a second multiplexer, having third and fourth input terminals and a second output terminal; and
a second LE includes a seventh LUT, an eighth LUT, a third adder, a fourth adder, a third multiplexer, having fifth and sixth input terminals and a third output terminal, and a fourth multiplexer, having seventh and eighth input terminals and a fourth output terminal; wherein,
each LUT is configured to perform as a fracturable LUT that is configured to enable a respective LE to implement n number of input logic functions in a first mode and two times (n−1) number of input logic functions in a second mode.