Digitally controlled oscillators
View Patent ↗Oscillator circuitry is provided that is based on a ring of inverters. The ring of inverters may be single-ended or differential inverters. Digitally controlled adjustable load capacitors may be provided at inverter outputs to tune the oscillator circuitry. Each digitally controlled adjustable load capacitor may be formed from multiple varactors connected in parallel. Each varactor may have a control input that receives a digital control signal. The digitally controlled adjustable load capacitors in a given oscillator may be adjusted in unison to produce the same capacitance value for each capacitor or may be adjusted individually so that they produce different capacitance values. The inverters may include common-mode-gain reduction features such as series-connected current sources, series-connected resistors, and cross-coupled negative feedback transistors.
1. A method of adjusting an output signal frequency in an oscillator formed from a ring of inverters coupled to adjustable load capacitors, wherein each capacitor of the adjustable load capacitors comprises a plurality of parallel-coupled varactors, wherein each varactor of the parallel-coupled varactors has a digital control input operable to receive a digital control signal, comprising:
applying a first digital control word formed from first digital control signals to a first of the adjustable load capacitors operable to direct that first capacitor to produce a first capacitance value, wherein applying the first digital control word to the first of the adjustable load capacitors comprises applying the first digital control signals to the digital control inputs of the parallel-coupled varactors of the first of the adjustable load capacitors;
applying a second digital control word formed from second digital control signals to a second of the adjustable load capacitors operable to direct that second capacitor to produce a second capacitance value that is different from the first capacitance value, wherein applying the second digital control word to the second of the adjustable load capacitors comprises applying the second digital control signals to the digital control inputs of the parallel-coupled varactors of the second of the adjustable load capacitors; and
ensuring that the first digital control word and the second digital control word contain respective numbers of logic high signals that differ by no more than one.
2. The method defined in claim 1 wherein the inverters comprise first and second differential inverters each having a positive output and a negative output to which respective ones of the adjustable load capacitors are coupled, wherein ensuring that the first digital control word and the second digital control word contain respective numbers of logic high signals that differ by no more than one comprises ensuring that the digital control word applied to the adjustable load capacitor coupled to the positive output of the first differential inverter and the digital control word applied to the adjustable load capacitor coupled to the negative output of the first differential inverter differ by no more than one.
3. A method of adjusting an output signal frequency in an oscillator formed from a ring of inverters coupled to adjustable load capacitors, comprising:
applying a first digital control signal to a first of the adjustable load capacitors operable to direct that first capacitor to produce a first capacitance value;
applying a second digital control signal to a second of the adjustable load capacitors operable to direct that second capacitor to produce a second capacitance value that is different from the first capacitance value, wherein each of the adjustable load capacitors comprises a plurality of parallel-coupled varactors having digital control inputs and wherein the digital control inputs of the varactors in each of the adjustable load capacitors are operable to receive a digital control signal that controls that adjustable load capacitor; and
when applying the first digital control signal and the second digital control signal respectively to the first and second adjustable load capacitors, ensuring that the first digital control signal and the second digital control signal contain respective numbers of logic high signals that differ by no more than one to minimize capacitance mismatch between the first and second capacitance values.