IP Library Granted Patent US 7,514,789
Granted Patent B1
US 7,514,789 · App. 12/147,411 · Granted Apr 7, 2009

Ball grid array package-to-board interconnect co-design apparatus

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Quick Facts
Patent No.
US 7,514,789
App. No.
12/147,411
Granted
Apr 7, 2009
Kind
B1
Abstract

A package-board co-design methodology preserves the signal integrity of high-speed signals passing from semiconductor packages to application PCBs. An optimal architecture of interconnects between package and PCB enhances the signal propagation, minimizes parasitic levels, and decreases electromagnetic interference from adjacent high frequency signals. The invention results in devices with superior signal quality and EMI shielding properties with enhanced capability for carrying data stream at multiple-gigabit per second bit-rates.

Claims (12)

1. An integrated circuit apparatus, comprising:

a ball grid array semiconductor package, the package having a package substrate with a board interface layer having board signal traces and ground/power points;

a printed circuit board comprising a package interface layer having package signal traces and ground/power points; and

a ball grid array interconnecting the package and board, the ball grid array comprising one or more signal balls interconnecting the package and board signal traces and ground/power balls interconnecting the package and board ground/power points;

wherein the ground/power balls of the ball grid array electromagnetically isolate the signal ball or signal ball pair of the ball grid array from other signal balls or signal ball pairs.

2. The apparatus of claim 1 , wherein the ground/power balls are ground balls.

3. The apparatus of claim 1 , wherein the ground/power balls are disposed about the signal ball or signal ball pair in a coaxial like format.

4. The apparatus of claim 3 , wherein the ground/power balls are disposed about the signal ball or signal ball pair in a hexagonal or octagonal pattern.

5. The apparatus of claim 1 , wherein the signal ball or signal ball pair are on a perimeter of the array and are electrically isolated from other signal balls or signal ball pairs by being surrounded by the ground/power balls to form a shielding cavity completed by the perimeter.

6. The apparatus of claim 1 , wherein a single signal ball is surrounded by ground/power balls.

7. The apparatus of claim 1 , wherein a pair of signal balls is surrounded by ground/power balls.

8. The apparatus of claim 1 , wherein a 50 ohm singled-ended or 100 ohm differential impedance of signal traces results.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061827/0686 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2022
From: ALTERA CORPORATION
To: INTEL CORPORATION
Reel/Frame 060778/0032 →