Memory elements with increased write margin and soft error upset immunity
View Patent ↗Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.
1. A memory element comprising:
two interconnected transistor sets that each provide a respective one of two nodes, wherein each of the two transistor sets comprises three transistors connected in series and wherein one of the transistors in each of the two transistor sets is turned off during write operations.
2. The memory element defined in claim 1 wherein the three transistors connected in series in at least one of the two interconnected transistor sets comprise two p-channel transistors and an n-channel transistor.
3. The memory element defined in claim 2 wherein in at least one of the two interconnected transistor sets a respective one of the two nodes is formed by a series connection between the n-channel transistor and one of the two p-channel transistors.
4. The memory element defined in claim 2 wherein the one of the transistors in each of the two transistor sets that is turned off during write operations comprises one of the two p-channel transistors.
5. The memory element defined in claim 1 wherein each of the three transistors in each of the two transistor sets has a gate and wherein the two transistor sets are interconnected via the two nodes and two of the three gates in each of the two transistor sets.
6. The memory element defined in claim 1 further comprising a first additional transistor set that provides a first redundant node, wherein the first redundant node helps the two nodes maintain stored data.
7. The memory element defined in claim 6 further comprising a second additional transistor set that provides a second redundant node, wherein the second redundant node helps the two nodes and the first redundant node maintain the stored data.
8. The memory element defined in claim 7 wherein each of the first and second additional transistor sets comprises two transistors connected in series.
9. The memory element defined in claim 7 wherein each of the first and second additional transistor sets comprises an n-channel transistor and a p-channel transistor.
10. The memory element defined in claim 1 wherein the three transistors connected in series in at least one of the two interconnected transistor sets comprise two n-channel transistors and a p-channel transistor.
11. The memory element defined in claim 10 wherein the one of the transistors in each of the two transistor sets that is turned off during write operations comprises one of the two n-channel transistors.