Memory circuit with PMOS access transistors
A memory circuit that includes a memory storage unit and access transistors coupled to the memory storage unit, where the access transistors include PMOS transistors, is described. In one implementation, the memory circuit further includes a bias clamp transistor coupled to the memory storage unit.
1. A memory circuit comprising:
a memory storage unit;
a first access transistor coupled to the memory storage unit, wherein the first access transistor is a p-channel metal oxide semiconductor (PMOS) transistor;
a bias clamp transistor coupled to the memory storage unit; and
pre-charging circuitry coupled to the bias clamp transistor,
wherein a body of the first access transistor is coupled to a supply voltage and wherein the bias clamp transistor isolates the pre-charging circuitry from the supply voltage,
wherein the memory storage unit comprises a first inverter, wherein the first inverter is a first complementary metal oxide semiconductor (CMOS) inverter including a first n-channel metal oxide semiconductor (NMOS) transistor coupled in series to a first PMOS transistor, wherein a reverse body bias (RBB) is applied to the first NMOS transistor, and further wherein the first PMOS transistor is a thick gate oxide (TGO) transistor.
2. The memory circuit of claim 1 , wherein the first access transistor is a read access transistor.
3. The memory circuit of claim 2 , further comprising:
a second access transistor, wherein the second access transistor is a PMOS transistor, further wherein the second access transistor is a write access transistor.
4. The memory circuit of claim 3 , wherein the write access transistor is coupled to a data line, further wherein the read access transistor is coupled to the data line.
5. The memory circuit of claim 1 , wherein the PMOS transistor has a high threshold voltage.
6. The memory circuit of claim 1 , wherein the memory storage unit further comprises:
a second inverter coupled to the first inverter,
wherein the second inverter is a second CMOS inverter including a second NMOS transistor coupled in series to a second PMOS transistor.
7. A programmable logic device including the memory circuit of claim 1 .
8. A digital system comprising a programmable logic device including the memory circuit of claim 1 .
9. A configuration random access memory (RAM) including the memory circuit of claim 1 .
10. The memory circuit of claim 1 , wherein the supply voltage has a higher magnitude than a supply voltage that is used for read/write operations in the memory circuit.
11. A memory circuit comprising:
a latch;
a first p-channel metal oxide semiconductor (PMOS) access transistor coupled to the latch, wherein the first PMOS access transistor is a read access transistor;
a second PMOS access transistor coupled to the latch, wherein the second PMOS access transistor is a write access transistor;
a bias clamp transistor coupled to the latch; and
pre-charging circuitry coupled to the bias clamp transistor,
wherein the bias clamp transistor isolates the pre-charging circuitry from a supply voltage applied to a body of the first PMOS access transistor,
wherein the latch comprises a first inverter, wherein the first inverter is a first complementary metal oxide semiconductor (CMOS) inverter including a first n-channel metal oxide semiconductor (NMOS) transistor coupled in series to a first PMOS transistor, wherein a reverse body bias (RBB) is applied to the first NMOS transistor, and further wherein the first PMOS transistor is a thick gate oxide (TGO) transistor.
12. The memory circuit of claim 11 , wherein the latch further comprises:
a second inverter coupled to the first inverter,
wherein the second inverter is a second CMOS inverter including a second NMOS transistor coupled in series to a second PMOS transistor.
13. The memory circuit of claim 11 , wherein the body of the first PMOS access transistor is coupled to the supply voltage and a body of the second PMOS access transistor is coupled to the supply voltage.
14. The memory circuit of claim 11 , wherein the supply voltage has a higher magnitude than a supply voltage that is used for read/write operations in the memory circuit.
15. A method comprising:
using a p-channel metal oxide semiconductor (PMOS) access transistor to provide access between a data line and a memory storage unit; and
using a bias clamp transistor to isolate a pre-charging circuitry from a supply voltage applied to a body of the PMOS access transistor,
wherein the memory storage unit includes a latch, wherein the latch includes a first inverter, wherein the first inverter is a first complementary metal oxide semiconductor (CMOS) inverter including a first n-channel metal oxide semiconductor (NMOS) transistor coupled in series to a first PMOS transistor, wherein a reverse body bias (RBB) is applied to the first NMOS transistor, and further wherein the first PMOS transistor is a thick gate oxide (TGO) transistor.
16. The method of claim 15 , wherein the latch further includes a second inverter coupled to the first inverter, and wherein the second inverter is a second CMOS inverter including a second NMOS transistor coupled in series to a second PMOS transistor.
17. The method of claim 15 , wherein the supply voltage has a higher magnitude than a supply voltage that is used for read/write operations in the memory storage unit.