Circuitry for reducing leakage current in configuration memory
Integrated circuits may include dual mode memory cells. Dual mode memory cells may be operated in a lookup-table mode or a memory mode. A dual mode memory cell may have configuration ports for supporting a configuration operation and user ports for supporting a user mode operation. When performing configuration operations in the memory mode, the configuration ports may be gated off to prevent existing user data from being accessed. Each column of memory cells may be arranged into groups. Each group of memory cells in a column may be connected to a respective local data line, which is connected to a global data line via a switch. The switch may be selectively activated to short the local data line to the global data line. Configured in this hierarchical data line architecture, leakage at the global data line can dramatically be reduced, and the memory cell read margin is improved.
1. An integrated circuit, comprising:
a first dual mode memory cell;
a second dual mode memory cell, wherein the first and second dual mode memory cells are operable in a configuration mode and a user memory mode, and wherein the first and second dual mode memory cells store user data bits when operating in the user memory mode and supply configuration bits that are different than the user data bits when operating in the configuration mode;
a local data line that is connected to the first dual mode memory cell and the second dual mode memory cell;
a global data line; and
a circuit that selectively couples the local data line to the global data line.
2. The integrated circuit of claim 1 , wherein the circuit comprises a pass gate transistor.
3. The integrated circuit of claim 1 , wherein the circuit comprises a bidirectional tristate buffer.
4. The integrated circuit of claim 1 , further comprising:
a third dual mode memory cell;
a fourth dual mode memory cell;
an additional local data line that is connected to the third dual mode memory cell and the fourth dual mode memory cell; and
an additional circuit that selectively couples the additional local data line to the global data line.
5. The integrated circuit of claim 1 , further comprising programmable logic circuitry controlled by the configuration bits.
6. The integrated circuit of claim 1 , wherein the configuration bits in the first and second dual mode memory cells are overwritten during device reconfiguration operations.
7. An integrated circuit, comprising:
a first dual mode memory cell;
a second dual mode memory cell, wherein the first and second dual mode memory cells are operable in a configuration mode and a user memory mode, and wherein the first and second dual mode memory cells each have a configuration port and a user port;
a local data line that is connected to the first dual mode memory cell and the second dual mode memory cell;
a global data line;
a circuit that selectively couples the local data line to the global data line; and
gating logic at the configuration port, wherein the configuration port is gated off by the gating logic while the first and second dual mode memory cells are operated in the user memory mode.
8. The integrated circuit of claim 7 , wherein the first and second dual mode memory cells are powered using a memory cell supply voltage and a ground power supply voltage, and wherein the configuration port is addressed using signals that swing between the ground power supply voltage and an overdrive voltage that is greater than the memory cell supply voltage.
9. The integrated circuit of claim 7 , wherein the gating logic comprises a logic AND gate.
10. A method for operating an integrated circuit, comprising:
operating a plurality of dual mode memory cells in a memory mode;
operating the plurality of dual mode memory cells in a lookup-table (LUT) mode that is different than the memory mode, wherein the plurality of dual mode memory cells is connected to a local data line, and wherein each dual mode memory cell in the plurality of dual mode memory cells has a user port for supporting a user mode operation and a configuration port for supporting a configuration operation;
with a circuit, selectively coupling the local data line to a global data line; and
gating the configuration port during the memory mode.
11. The method of claim 10 , further comprising:
not gating the configuration port during the LUT mode.
12. The method of claim 10 , wherein gating the configuration port comprises outputting an address signal at a ground power supply voltage level to at least one of the plurality of dual mode memory cells.
13. The method of claim 10 , further comprising:
with a control block, selectively outputting an asserted control signal to activate the circuit.
14. The method of claim 10 , further comprising using the global data line to load data into the plurality of dual mode memory cells.