Method of mapping a user design defined for a user design cycle to an IC with multiple sub-cycle reconfigurable circuits

1. A method of implementing an integrated circuit (IC), the method comprising:

a) receiving a first IC design that performs a set of user functions during a particular user design cycle, wherein each user design cycle comprises a plurality of sub-cycles of a second IC design comprising a plurality of reconfigurable circuits;

b) assigning the user functions to the plurality of sub-cycles; and

c) assigning each user function performed during a particular sub-cycle to a particular reconfigurable circuit of the second IC design,

wherein each particular reconfigurable circuit may perform a plurality of operations for a plurality of user functions of the first IC design in a plurality of different sub-cycles.

2. The method of claim 1 , wherein a plurality of reconfigurable circuits are reconfigurable logic circuits.

3. The method of claim 2 , wherein each particular reconfigurable logic circuit is for receiving input data sets and configuration data sets and performing a particular set of functions on the input data sets, wherein each configuration data set specifies a particular function that the particular reconfigurable logic circuit has to perform on an input data set.

4. The method of claim 2 , wherein a plurality of reconfigurable circuits are reconfigurable interconnect circuits, wherein each particular reconfigurable interconnect circuit comprises an input terminal set, an output terminal set, and a plurality of connection schemes for communicatively coupling the particular reconfigurable interconnect circuit's input terminal and output terminal sets.

5. The method of claim 4 , wherein a plurality of reconfigurable interconnect circuits are multiplexers.

6. The method of claim 4 , wherein a plurality of reconfigurable interconnect circuits are decoders.

7. The method of claim 4 , wherein each particular reconfigurable interconnect circuit is for receiving different configuration data sets and, based on the configuration data sets, selecting a connection scheme that connects the particular reconfigurable interconnect circuit's input terminal and output terminal sets.

8. The method of claim 7 , wherein a plurality of reconfigurable interconnect circuits are for configurably coupling the reconfigurable logic circuits.

9. The method of claim 7 , wherein a plurality of reconfigurable interconnect circuits are for configurably coupling other interconnect circuits.

10. The method of claim 1 , wherein the first IC design does not comprise configurable circuits.

11. The method of claim 1 , wherein the first IC design comprises configurable circuits.

12. A computer readable medium storing a computer program for implementing an integrated circuit (“IC”), the computer program executable by at least one processor of a computer, the computer program comprising:

a) a set of instructions for receiving a first IC design that performs a set of user functions during a particular user design cycle, wherein each user design cycle comprises a plurality of sub-cycles of a second IC design comprising a plurality of reconfigurable circuits;

b) a set of instructions for assigning the user functions to a plurality of sub-cycles; and

c) a set of instructions for assigning each user function performed during a particular sub-cycle to a particular reconfigurable circuit of the second IC design,

wherein each particular reconfigurable circuit may perform a plurality of operations for a plurality of user functions of the first IC design in a plurality of different sub-cycles.

13. The computer readable medium of claim 12 , wherein a plurality of reconfigurable circuits are reconfigurable logic circuits.

14. The computer readable medium of claim 13 , wherein each particular reconfigurable logic circuit is for receiving input data sets and configuration data sets and performing a particular set of functions on the input data sets, wherein each configuration data set specifies a particular function that the particular reconfigurable logic circuit has to perform on an input data set.

15. The computer readable medium of claim 13 , wherein a plurality of reconfigurable circuits are reconfigurable interconnect circuits, wherein each particular reconfigurable interconnect circuit comprises an input terminal set, an output terminal set, and a plurality of connection schemes for communicatively coupling the particular reconfigurable interconnect circuit's input terminal and output terminal sets.

16. The computer readable medium of claim 15 , wherein each particular reconfigurable interconnect circuit is for receiving different configuration data sets and, based on the configuration data sets, selecting a connection scheme that connects the particular reconfigurable interconnect circuit's input terminal and output terminal sets.

17. The computer readable medium of claim 15 , wherein a plurality of reconfigurable interconnect circuits are for configurably coupling the reconfigurable logic circuits.

18. The computer readable medium of claim 17 , wherein a plurality of reconfigurable interconnect circuits are for configurably coupling other interconnect circuits.

19. The computer readable medium of claim 12 , wherein the first IC design does not comprise configurable circuits.

20. The computer readable medium of claim 12 , wherein the first IC design comprises configurable circuits.