Stacked die network-on-chip for FPGA
View Patent ↗A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.
1. A method of making a device, the method comprising:
receiving, at a computer system, a design;
selecting, based on the design, at least one field programmable gate array (FPGA) die layer from an FPGA library;
selecting at least one network-on-chip (NoC) die layer from a NoC library; and
connecting the at least one FPGA die layer and the at least one NoC die layer, wherein the FPGA die layer includes a multiplexer, the multiplexer having a first input provided by the NoC die layer, a second input provided by the FPGA die layer, and an output implemented in the FPGA die layer.
2. The method of claim 1 , wherein the connecting includes electrically connecting the at least one FPGA die layer to the at least one NoC die layer.
3. The method of claim 2 , wherein the electrically connecting comprises forming through silicon vias between the at least one NoC and the at least one FPGA die layers.
4. The method of claim 1 , further comprising:
logic synthesizing based on the design;
placing and routing a plurality of logic cells on a plurality of logic elements of the device;
verifying a plurality of timing constraints of the device; and
programming the connected die layers.
5. The method of claim 1 , further comprising:
receiving a signal from the at least one NoC die layer; and
outputting a planar output signal by multiplexing the signal with a planar input received from the at least one FPGA die layer.
6. The method of claim 1 , further comprising:
receiving a plurality of planar input signals;
generating a vertical output signal by multiplexing the plurality of planar input signals, wherein the multiplexing is performed based on a select signal; and
outputting the vertical output signal to the at least one NoC die layer.
7. The method of claim 1 , further comprising implementing a plurality of 3-D switches on the at least one NoC die layer.
8. The method of claim 1 , further comprising using a plurality of 3-D vertical interconnects to connect a segment of the at least one FPGA die layer with an interconnect switch on the at least one NoC die layer.
9. The method of claim 1 , further comprising creating a plurality of segments by segmenting the at least one FPGA die layer.
10. The method of claim 9 , wherein each segment has the same size or at least one segment of the plurality of segments has a different size than the remaining segments of the plurality of segments.
11. The method of claim 1 further comprising:
at least one of a plurality of connectors connecting the NoC die layer and the FPGA die layer, wherein the NoC die layer includes interconnection circuitry operable to connect the FPGA die layer.
12. A device made and used by the process of:
receiving a design of the device;
selecting, based on the design, at least one field programmable gate array (FPGA) die layer from an FPGA library;
selecting at least one network-on-chip (NoC) die layer from a NoC library; and
connecting the at least one FPGA die layer and the at least one NoC die layer, wherein the FPGA die layer includes a multiplexer, the multiplexer having a first input provided by the NoC die layer, a second input provided by the FPGA die layer, and an output implemented in the FPGA die layer.
13. The device of claim 12 , made by the connecting that includes electrically connecting the at least one FPGA die layer to the at least one NoC die layer.
14. The device of claim 12 , made by the electrically connecting that includes forming through silicon vias between the at least one NoC and at least one FPGA die layers.
15. The device of claim 12 , further made by the process of:
logic synthesizing based on the design;
placing and routing a plurality of logic cells on a plurality of logic elements of the device;
verifying a plurality of timing constraints of the device; and
programming the connected die layers.
16. The device of claim 12 , further used by the process of:
receiving a signal from the at least one NoC die layer; and
outputting a planar output signal by multiplexing the signal with a planar input received from the at least one FPGA die layer.
17. The device of claim 12 , further used by the process of:
receiving a plurality of planar input signals;
generating a vertical output signal by multiplexing the plurality of planar input signals, wherein the multiplexing is performed based on a select signal; and
outputting the vertical output signal to the at least one NoC die layer.
18. The device of claim 12 , further made by the process of implementing a plurality of 3-D switches on the at least one NoC die layer.
19. The device of claim 12 , further made by the process of using a plurality of 3-D vertical interconnects to connect a segment of the at least one FPGA die layer with an interconnect switch on the at least one NoC die layer.
20. The device of claim 12 , further made by the process of creating a plurality of segments by segmenting the at least one FPGA die layer.
21. The device of claim 20 , wherein each segment has the same size or at least one segment of the plurality of segments has a different size than the remaining segments of the plurality of segments.