Apparatus and Methods for Adjusting Performance of Programmable Logic Devices
A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).
1 - 18 . (canceled)
19 . A programmable logic device (PLD), comprising:
a control circuitry;
a body-bias generator coupled to the control circuitry, the body-bias generator configured to set a body bias of a transistor within the programmable logic device (PLD); and
a variable impedance device coupled to the control circuitry, the variable impedance device configured to control power dissipation of a first circuit within the programmable logic device (PLD).
20 . The programmable logic device (PLD) according to claim 19 , wherein the first circuit comprises a circuit unused in an electronic circuit implemented by the programmable logic device (PLD).
21 . The programmable logic device (PLD) according to claim 20 , wherein the variable impedance device comprises a field-effect transistor (FET).
22 . The programmable logic device (PLD) according to claim 21 , wherein the body-bias generator is configured to set the body bias of the transistor so as to avoid thermal runaway within the programmable logic device (PLD).
23 . The programmable logic device (PLD) according to claim 21 , wherein the body-bias generator is further configured to adjust the body bias of the transistor so as to trade off performance and power consumption of the transistor.
24 . The programmable logic device (PLD) according to claim 23 , wherein the body-bias generator is further configured to adjust the body bias of the transistor so as to optimize the tradeoff between the performance and power consumption of the transistor.
25 . The programmable logic device (PLD) according to claim 19 , wherein the variable impedance device is further configured to shut down the first circuit by interrupting a supply of power to the first circuit.
26 . The programmable logic device (PLD) according to claim 25 , wherein the supply of power to the first circuit is provided by a supply-voltage circuit within the programmable logic device (PLD).
27 . A programmable logic device (PLD), comprising:
a temperature sensor, the temperature sensor configured to sense a temperature of a first circuit in the programmable logic device (PLD);
a body-bias generator configured to set a body bias of a set of transistors in response to a control signal; and
a control circuit coupled to the temperature sensor and the body-bias generator, the control circuit configured to provide the control signal in response to a signal received from the temperature sensor.
28 . The programmable logic device (PLD) according to claim 27 , wherein the control circuit is further configured to provide the control signal so as to avoid thermal runaway in the set of transistors.
29 . The programmable logic device (PLD) according to claim 27 , wherein the control circuit is further configured to provide the control signal so as to trade off performance and power consumption of the set of transistors.
30 . The programmable logic device (PLD) according to claim 29 , wherein the control circuit is further configured to provide the control signal so as to optimize the tradeoff between the performance and power consumption of the set of transistors.
31 . The programmable logic device (PLD) according to claim 27 , wherein the set of transistors resides in the first circuit.
32 . The programmable logic device (PLD) according to claim 27 , wherein the control circuit is further configured to derive the control signal from a reference signal and a signal received from the temperature sensor.
33 - 80 . (canceled)