Forward error correction with configurable latency
View Patent ↗A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target Bit Error Rate (BER) against an actual BER and adjusts the size of a configurable buffer such that the target BER may be achieved when utilizing the smallest buffer size possible. When errors are corrected without the utilization of each of the configurable buffer locations, the algorithm reduces the size of the buffer by y buffer locations; the algorithm may continue to successively reduce the size of said buffer until the minimum number of buffer locations are utilized to achieve the target BER. If the buffer locations have been reduced such that the buffer size is too small and the target BER cannot be achieved, the algorithm may increase the size of the buffer until the minimum number of buffer locations are utilized to achieve the target BER.
1. A method for forward error correction using a configurable buffer, the method comprising:
selecting a number of configurable buffer locations for storing received data associated with a target bit error rate;
storing the received data in the selected number of configurable buffer locations;
computing a bit error rate based on forward error correction of the stored data;
comparing the bit error rate with the target bit error rate; and
reducing the selected number of configurable buffer locations for storing the received data by a first amount if the bit error rate achieves the target bit error rate.
2. The method of claim 1 further comprising increasing the selected number of configurable buffer locations for storing the received data by a second amount if the bit error rate does not achieve the target bit error rate.
3. The method of claim 1 , wherein the bit error rate achieves the target bit error rate if the bit error rate is not greater than the target bit error rate.
4. The method of claim 1 , wherein the selected number of configurable buffer locations corresponds to latency associated with achieving the target bit error rate.
5. The method of claim 1 , wherein the selected number of configurable buffer locations is a maximum number of available configurable buffer locations.
6. The method of claim 1 , wherein the forward error correction code is a Bose Ray-Chaudhuri (BCH) code.
7. An apparatus for forward error correction, the apparatus comprising:
a configurable buffer, wherein a number of buffer locations of the configurable buffer are selected for storing received data associated with a target bit error rate;
an error monitor for computing a bit error rate based on forward error correction of the stored data; and
logic circuitry for:
comparing the bit error rate with the target bit error rate; and
reducing the selected number of buffer locations for storing the received data by a first amount if the bit error rate achieves the target bit error rate.
8. The apparatus of claim 7 , wherein the logic circuitry increases the selected number of configurable buffer locations for storing the received data by a second amount if the bit error rate does not achieve the target bit error rate.
9. The apparatus of claim 7 , wherein the bit error rate achieves the target bit error rate if the bit error rate is not greater than the target bit error rate.
10. The apparatus of claim 7 , wherein the selected number of configurable buffer locations corresponds to latency associated with achieving the target bit error rate.
11. The apparatus of claim 7 , wherein the selected number of configurable buffer locations is a maximum number of available configurable buffer locations.
12. The apparatus of claim 7 , wherein the forward error correction code is a Bose Ray-Chaudhuri (BCH) code.
13. The apparatus of claim 7 , wherein the target bit error rate is received by the logic circuitry with the received data.
14. A method for forward error correction with configurable latency, the method comprising:
selecting a size of a configurable buffer for storing received data associated with a target bit error rate;
storing the received data in the configurable buffer of the selected size;
computing a bit error rate based on forward error correction of the stored data; and
adjusting the size of the configurable buffer based on a comparison between the target bit error rate with the bit error rate.
15. The method of claim 14 further comprising reducing the size of the configurable buffer by a first amount if the bit error rate achieves the target bit error rate.
16. The method of claim 15 further comprising increasing the size of the configurable buffer by a second amount if the bit error rate does not achieve the target bit error rate.
17. The method of claim 16 , wherein the first amount is different from the second amount.
18. The method of claim 15 , wherein the bit error rate achieves the target bit error rate if the bit error rate is not greater than the target bit error rate.
19. The method of claim 14 , wherein the selected size of the configurable buffer corresponds to the maximum size of the configurable buffer.
20. The method of claim 14 , wherein the forward error correction code is a Bose Ray-Chaudhuri (BCH) code.