Patent Assignment
Reel/Frame 061359/0223
Change of Name
Recorded: 2022-10-10
Pages: 3
Assignor
INTEL TECHNOLOGY OF CANADA, LTD.
Executed: 2021-06-25
Assignee
INTEL TECHNOLOGY OF CANADA, ULC
450 SW MARINE DRIVE, UNIT 700, VANCOUVER, V5X 4V2, CANADA
Covered Properties
(40)
Complementary Architecture for Field-Programmable Gate Arrays
Patent:
5,537,341 →
Application:
08/387,402 →
Automatic Generation of Programmable Logic Device Architectures
Patent:
6,631,510 →
Application:
09/429,013 →
Heterogeneous Interconnection Architecture for Programmable Logic Devices
Patent:
6,590,419 →
Application:
09/478,097 →
Heterogeneous Interconnection Architecture for Programmable Logic Devices
Automatic Generation of Programmable Logic Device Architectures
Patent:
7,051,313 →
Application:
10/641,193 →
Skew-Correcting Apparatus Using Dual Loopback
Skew-Correcting Apparatus Using Iterative Approach
Skew-Correcting Apparatus Using External Communications Element
Context-Sensitive Overhead Processor
Forward Error Correction Codec
Method of Accessing Stored Information in Multi-Framed Data Transmissions.
Method of Performing Serial Functions in Parallel
Application:
12/431,781 →
Publication:
US 2010/0217960
Pseudo-random bit sequence generator
Method of Multiple Lane Distribution (Mld) Deskew
Strict-Sense Minimal Spanning Switch Non-Blocking Architecture
Method and Apparatus for Deskewing Data Transmissions
Method and apparatus for error-correction in and processing of GFP-T superblocks
2D Product Code and Method for Detecting False Decoding Errors
Method for finding starting bit of reference frames for an alternating-parity reference channel
Forward Error Correction with Configurable Latency
Context-Sensitive Overhead Processor
Method of Multiple Lane Distribution (Mld) Deskew
Method of Accessing Stored Information in Multi-Framed Data Transmissions
Strict-Sense Minimal Spanning Switch Non-Blocking Architecture
2D Product Code and Method for Detecting False Decoding Errors
Method of Multiple Lane Distribution (Mld) Deskew
Patent:
8,705,581 →
Application:
13/750,377 →
Context-Sensitive Overhead Processor
Forward Error Correction with Configurable Latency
Strict-Sense Minimal Spanning Switch Non-Blocking Architecture
Method and Apparatus for Deskewing Data Transmissions
Method for Finding Starting Bit of Reference Frames for an Alternating-Parity Reference Channel
Forward Error Correction with Configurable Latency
Method of Multiple Lane Distribution (Mld) Deskew
Patent:
9,281,911 →
Application:
14/243,725 →
Pseudo-Random Bit Sequence Generator
Forward Error Correction with Configurable Latency
Forward error correction CODEC
Application:
60/994,314 →
Method for Multiple Lane Distribution (MLD) De-Skew
Application:
61/154,058 →
Pipelined Logic Tree
Application:
61/154,061 →
Strict-Sense Minimal Spanning Switch Non-Blocking Architecture
Application:
61/227,923 →
2D Product Code and Method for Detecting False Decoding Errors
Application:
61/255,271 →
Related Assignments
(7)
Other recorded transfers of the patents in this record — the chain of ownership.
Change of Name
May 26, 2021
From: ALTERA NEWFOUNDLAND TECHNOLOGY CORP.
To: ALTERA CANADA CO.
Reel/Frame 056398/0428 →
Merger and Change of Name
Aug 29, 2022
From: ALTERA CANADA LTD.; INTEL OF CANADA, LTD.
To: INTEL OF CANADA, LTD.
Reel/Frame 060921/0206 →
Change of Name
Aug 29, 2022
From: ALTERA CANADA CO.
To: ALTERA CANADA LTD.
Reel/Frame 061333/0007 →
Change of Name
Aug 29, 2022
From: INTEL OF CANADA, LTD.
To: INTEL TECHNOLOGY OF CANADA, LTD.
Reel/Frame 061334/0500 →
Assignment of Assignor's Interest
Oct 10, 2022
From: INTEL TECHNOLOGY OF CANADA, ULC
To: INTEL CORPORATION
Reel/Frame 061368/0947 →
Assignment of Assignor's Interest
Jan 19, 2024
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 066353/0886 →
Security Interest
Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →