Method and apparatus for deskewing data transmissions
View Patent ↗The present invention discloses a method and apparatus for addressing the issue of clock skew in a data signal while making efficient use of space on an integrated chip (IC) by utilizing a physical delay line controlled by a state machine in conjunction with pre-requisite chip architecture. The pre-requisite chip architecture samples the incoming data signal in response to a clocking signal input from the physical delay line; the physical delay line responds to commands from the state machine to increment the delay of the physical delay line to produce samples which describe the incoming data signal and delineate its data valid window.
1. A method for correcting skew in at least one transmitting lane, in a data transmission system, comprising:
a. a data signal comprising plurality of data, wherein said data signal is transmitted across a transmitting lane, whereby said data signal further comprises a plurality of transitions from a first state to a second state;
b. a plurality of data valid windows, wherein each of said plurality of data valid windows comprises a stable portion of said data signal located between a first transition of said data signal and a second transition of said data signal;
c. a timing signal for said data signal comprising a plurality of latching edges, wherein said plurality of latching edges activate at least one circuitry element, whereby said circuitry element obtains a plurality of data samples by sampling said data signal at successive intervals of time; and
d. a state machine to implement an algorithm to determine a mean length of each of said plurality of data valid windows and further determine a median position of said mean length, wherein said algorithm determines said mean length and said median position through processing said plurality of data samples,
wherein each of said plurality of data samples indicates the stability of said data signal at one of a plurality of intervals in one of a plurality of cycles of said data signal,
whereby said timing signal is adjusted by said state machine to allow each of said plurality of latching edges to occur in said median position of said mean length of said plurality of data valid windows.
2. The method of claim 1 , wherein delay is added to said timing signal by a physical delay element to adjust the position of said plurality of latching edges in relation to said data signal.
3. The method of claim 2 , wherein said state machine issues a plurality of requests for successive iterations of delay from said physical delay element, wherein said plurality of requests produces said plurality of samples.
4. The method of claim 3 , wherein said state machine requests a further iteration of delay from said physical delay element to align each of said plurality of latching edges with said median position in each of said data valid windows.
5. The method of claim 1 , wherein said circuitry element is a plurality of flip-flops, said plurality of flip-flops being connected in series.
6. An apparatus for correcting skew in at least one transmitting lane, in a data transmission system, comprising:
a. an input data signal comprising a plurality of data, wherein said input data signal is transmitted across a transmitting lane, whereby said input data signal further comprises a plurality of transitions from a first state to a second state;
b. a plurality of data valid windows, wherein each of said plurality of data valid windows comprises a stable portion of said input data signal located between a first transition of said input data signal and a second transition of said input data signal;
c. an input timing signal for said input data signal comprising a plurality of latching edges;
d. deserializer circuitry, wherein said deserializer circuitry receives said input data signal and samples said input data signal on said plurality of latching edges to obtain a plurality of data samples from said input data signal, whereby said plurality of data samples is output by said deserializer circuitry as an output data signal, wherein said output data signal is timed by an output timing signal; and
e. a state machine to request a plurality of iterations of delay from a physical delay element, wherein said physical delay element adds delay to said input timing signal to produce said plurality of iterations of delay in response to said state machine, whereby said state machine processes said plurality of data samples output by said deserializer circuitry as said output data signal.
7. The apparatus of claim 6 , wherein said deserializer circuitry is a serial-to-parallel deserializer circuitry.
8. The apparatus of claim 7 , wherein said serial-to-parallel deserializer circuitry comprises an n-bit demultiplexer, wherein n is a number of bits to be transmitted in parallel in said output data signal.
9. The apparatus of claim 6 , wherein said output timing signal is produced by an n-clock divider connected to said input timing signal after said input timing signal has been delayed by said physical delay element.
10. The apparatus of claim 6 , wherein said state machine implements an algorithm to determine a mean length of said plurality of data valid windows and further determine a median position of said mean length, wherein said algorithm determines said mean length and said median position through processing said plurality of data samples, whereby each of said plurality of data samples indicates the stability of said input data signal at one of a plurality of intervals of said input data signal.