Patent Assignment
Reel/Frame 073431/0309
Security Interest
Recorded: 2025-09-12
Pages: 229
Assignor
ALTERA CORPORATION
Executed: 2025-09-12
Assignee
BARCLAYS BANK PLC, AS COLLATERAL AGENT
400 JEFFERSON PARK, WHIPPANY, NEW JERSEY, 07981
Covered Properties
(2165)
Techniques For Booting A Compute Integrated Circuit Using A Boot Management Controller In A Processing Integrated Circuit
Application:
17/954,698 →
Publication:
US US20230035058A1
Virtual Multi-Port Memory Processors, Methods, Systems, and Instructions
Application:
18/391,518 →
Publication:
US US20240126558A1
Flexible Circuit for Real and Complex Filter Operations
Application:
17/957,339 →
Publication:
US US20240113699A1
Latent Supplementary Protocol for Enhancing Performance & Functionality of Communication Systems
Application:
19/043,924 →
Publication:
US US20250184205A1
Power Savings by Register Insertion in Large Combinational Circuits
Application:
17/957,235 →
Publication:
US US20230027064A1
Efficient Triangular Systolic Array-Based Matrix Inversion
Application:
18/217,011 →
Publication:
US US20230342418A1
Techniques For Assessing Health Of Configurable Logic Circuits
Application:
18/475,199 →
Publication:
US US20240012972A1
Optical Co-Packaging on a Glass Substrate with 3D Die-Stacking
Application:
18/478,871 →
Publication:
US US20250110270A1
Intelligent Suggestions for CAD-Based Design Entry
Application:
18/398,699 →
Publication:
US US20240126960A1
Machine Learning Training Architecture for Programmable Devices
Application:
19/069,183 →
Publication:
US US20250199762A1
Techniques For Output Control During Update Of An Integrated Circuit
Application:
18/474,376 →
Publication:
US US20250105847A1
FPGA Specialist Processing Block for Machine Learning
Application:
19/226,027 →
Publication:
US US20250291596A1
Pipelined Galois Counter Mode Hash Circuit
Application:
18/129,709 →
Publication:
US US20230239136A1
Software Assisted Hardware Offloading Cache Using FPGA
Application:
18/478,602 →
Publication:
US US20240037037A1
Simultaneous Configuration of Programmable Logic Fabric and Disaggregated Dies
Application:
18/478,537 →
Publication:
US US20250111117A1
In-Field Droop Measurement and Compensation for Coherent Optical Transceiver
Application:
18/397,240 →
Publication:
US US20250219735A1
Translation Circuitry for Access Control Identifier Mechanisms
Application:
18/478,661 →
Publication:
US US20240056448A1
Thermal-Aware Programmable Logic Device-Based Programming
Application:
18/398,709 →
Publication:
US US20240126228A1
Methods and Apparatus to Expose a Microservice to a Software Layer
Application:
19/199,012 →
Publication:
US US20250272166A1
Micro Through-Silicon via for Transistor Density Scaling
Application:
18/824,468 →
Publication:
US US20240429131A1
FPGA Processing Block for Machine Learning or Digital Signal Processing Operations
Application:
17/358,923 →
Publication:
US US20210326111A1
Temperature Control Systems And Methods For Integrated Circuits
Application:
17/703,181 →
Publication:
US US20220215147A1
Built-In-Self-Test Circuits And Methods In Sectors Of Integrated Circuits
Application:
17/747,808 →
Publication:
US US20220277799A1
Memory Circuits And Methods With Write Assist
Application:
17/553,439 →
Publication:
US US20220108733A1
Grid-Based Interconnect System for Modular Integrated Circuit Systems
Application:
17/856,193 →
Publication:
US US20220336415A1
System, Method and Apparatus for Race-Condition True Random Number Generator
Application:
17/541,247 →
Publication:
US US20220100475A1
Input Output Banks of a Programmable Logic Device
Application:
18/091,626 →
Publication:
US US20230140547A1
Method and Apparatus for Enhancement of Common Mode Rejection on Coherent Optic Receivers
Application:
17/979,234 →
Publication:
US US20240146416A1
Undercut Design with a Bonded Base Cover for Friendly Assembly and Effective Thermal Tuning of Micro-Ring Resonator (Mrr) in Open Cavity Photonic Integrated Chips (Ocpic)
Processing Module, Integrated Development Environment, Methods, and Program Codes
Application:
17/643,852 →
Publication:
US US20220171659A1
Interface/Unicast for Test Content, Firmware, and Software Delivery
Accelerator Architecture on a Programmable Platform
Systems and Methods for Dynamic Power and Thermal Management for Programmable Logic Devices
Output Driver Circuits And Methods With Hot-Socket Protection
Application:
18/763,451 →
Publication:
US US20240356548A1
Multiplier Circuit with Carry-Based Partial Product Encoding
Application:
18/620,683 →
Publication:
US US20250251910A1
Acceleration of Evolutionary Algorithms through FPGA-GPU Hybrid
Application:
18/991,073 →
Publication:
US US20250124306A1
Integrated Circuit Aging Tracking and Compensation
Application:
18/991,041 →
Publication:
US US20250125803A1
Detecting and Handling Timing Anomalies Using Optimized Time of Days (ToDs) in a Multiclock Domain PTP Architecture
Application:
18/991,007 →
Publication:
US US20250150191A1
Circuits And Methods For Exchanging Data Coherency Traffic Through Multiple Interfaces
Dynamic Initiator Throttling in Network-on-Chip
Application:
19/004,255 →
Publication:
US US20250139047A1
Circuits And Methods For Generating Adjustable Signal Pulses That Control Writes To Memory Cells
Application:
18/904,611 →
Publication:
US US20250022495A1
Crossbar Switch Circuits And Methods In Integrated Circuits
Application:
18/915,782 →
Publication:
US US20260106619A1
Tensor Circuits And Methods For Multiplying With Sparse Weights
Application:
19/297,343 →
Publication:
US US20250371103A1
Networks-On-Chip For Configuration And Emulation Of Integrated Circuits
Application:
19/253,252 →
Publication:
US US20250321922A1
Scalable Thermal Diode Implementation in Monolithic and Multi-Die FPGAs
Application:
19/251,058 →
Publication:
US US20250323111A1
Configurable Storage Circuits And Methods
Application:
18/746,853 →
Publication:
US US20240337692A1
Circuits And Methods For Direct Memory Access Using A Network-On-Chip
Application:
18/945,209 →
Publication:
US US20260133922A1
Circuits And Methods For Multiplication Using Digital Signal Processing Blocks
Application:
18/982,252 →
Publication:
US US20260169692A1
Circuits And Methods For Systolic Memory
Application:
19/307,479 →
Publication:
US US20250391450A1
Systems and Methods for Bitstream Authentication
Application:
19/250,470 →
Publication:
US US20250323802A1
Retiming and Overclocking of Large Circuits
Application:
17/956,565 →
Publication:
US US20230018414A1
Programmable Input And Output Interfaces In Processing Integrated Circuits For Servers And Other Devices
Techniques For Arranging Conductive Pads In Electronic Devices
Application:
18/543,749 →
Publication:
US US20240120302A1
Electrostatic Discharge Protection (Esd) Circuitry Including Esd Circuit and Output Driver
Application:
18/372,260 →
Publication:
US US20250107246A1
Systems and Methods for Efficient Convergence of Network-Based Clock
Application:
63/714,010 →
FPGA Compiler Flow for Heterogeneous Programmable Logic Elements
Application:
18/401,026 →
Publication:
US US20240184966A1
Techniques For Shifting Signal Transmission To Compensate For Defects In Pads In Integrated Circuits
Application:
18/539,193 →
Publication:
US US20240113014A1
Stacked Package Design for More Reliable Fiber Coupling to Photonic Integrated Circuit
Application:
18/343,175 →
Publication:
US US20250004206A1
Block Number Conversion
Application:
18/401,426 →
Publication:
US US20250208865A1
Fast Fpga Compilation from Software Flows Through Partial Reconfiguration and Hardened Network-On-Chip
Application:
18/191,789 →
Publication:
US US20230237230A1
Low-Power High-Performance Clock Path Architecture
Application:
18/324,872 →
Publication:
US US20240393824A1
Techniques For Reducing Filter Distortion In Data Using Emphasis
Techniques For Configuring Computing Nodes In A Computing System
Application:
18/390,609 →
Publication:
US US20240126969A1
Circuit Systems And Methods For Transmitting Signals Between Devices
Application:
18/216,867 →
Publication:
US US20230342309A1
Systems And Methods For Correcting Errors in Code For Circuit Designs
Application:
18/122,612 →
Publication:
US US20230222275A1
Die-to-Die Power Delivery
Application:
17/957,217 →
Publication:
US US20230024662A1
Systems And Methods For Selecting Decoupling Capacitance Using A Power Jumper Circuit
Application:
18/207,842 →
Publication:
US US20230334212A1
Programmable Device-Based Accelerator Framework for Virtualized Environments
Application:
18/478,683 →
Publication:
US US20240031457A1
Systems And Methods For Thermal Monitoring In Integrated Circuits
Application:
18/476,702 →
Publication:
US US20240027279A1
Concept for Orchestration of Microservices
Application:
17/934,581 →
Publication:
US US20240281220A2
System and Methods for Closed Loop Doppler Tracking in Inter-Satellite Links
Application:
17/972,965 →
Publication:
US US20240235665A9
Circuits And Methods For Converting Between Data Formats And Data Filtering
Application:
18/526,940 →
Publication:
US US20240113730A1
Coherency Domain Cacheline State Tracking
Application:
18/478,621 →
Publication:
US US20240037038A1
Power and Temperature Management of Devices
Application:
17/955,183 →
Publication:
US US20230037609A1
Embedded Network on Chip Accessible to Programmable Logic Fabric of Programmable Logic Device in Multi-Dimensional Die Systems
Application:
18/797,325 →
Publication:
US US20240396555A1
Scalable Receiver Architecture for Silicon Photonic Links
Molded Fiber Connector Assembly for Pluggable Optical Mcp
Application:
17/125,497 →
Publication:
US US20220196939A1
Apparatus, Device, Method, and Computer Program for Generating Logic to be Performed by Computing Circuitry of a Computing Architecture
Circuits And Methods For Controlling Debugging Firmware In Integrated Circuit Devices
SYSTEMS AND METHODS FOR UCIe-AIB CHIPLET INTERFACE INTEROPERABILITY
Application:
18/075,183 →
Publication:
US US20230096585A1
Application-Based Dynamic Heterogeneous Many-Core Systems and Methods
Application:
17/403,627 →
Publication:
US US20220137986A1
Block Number Dot Product
Application:
18/401,423 →
Publication:
US US20250208864A1
Integrated Circuits with Machine Learning Extensions
Systems And Methods For Processor Circuits
Post-Quantum Cryptography Signature Verification
Application:
18/157,272 →
Publication:
US US20240223381A1
Logic Fabric Based on Microsector Infrastructure with Data Register Having Scan Registers
Application:
18/621,940 →
Publication:
US US20240241650A1
Block-Wise Pruning of Weights in Deep Neural Network
Application:
18/358,571 →
Publication:
US US20230368030A1
Security on Die-to-Die Interconnect
Application:
17/711,779 →
Publication:
US US20220229941A1
Systems and Methods for Calculating Large Polynomial Multiplications
Application:
17/560,838 →
Publication:
US US20220188072A1
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers
Application:
18/222,989 →
Publication:
US US20230359695A1
Embedded Multi-Die Interconnect Bridge with Improved Power Delivery
Application:
18/128,964 →
Publication:
US US20230238356A1
Integrity-Based Implementation of Content Using Digitally Signed Secure Quick Response Code
Application:
18/058,475 →
Publication:
US US20240171403A1
Programmable Logic Device with Integrated Network-On-Chip
Application:
17/690,994 →
Publication:
US US20220224656A1
Techniques for Monitoring and Control of High Speed Serial Communication Link
Fiber Array Unit (Fau) Designs to Enable a Higher Io Bandwidth Per Unit Length and Higher Fiber Density
Application:
17/889,233 →
Publication:
US US20240061192A1
Hazard Mitigation for Lightweight Processor Cores
System, Method and Apparatus for Peer-to-Peer Communication
Application:
17/682,015 →
Publication:
US US20220269433A1
Systems And Methods For Configurable Interface Circuits
Dynamic Loadlines for Programmable Fabric Devices
Method and System for Efficient Partitioning and Construction of Graphs for Scalable High-Performance Longest Prefix Matching
Application:
18/751,034 →
Publication:
US US20240354305A1
Adjustment of Fpga System Design Using Language-Based Machine Learning Models
Application:
18/896,267 →
Publication:
US US20250013823A1
Virtual Platform Management for FPGA
Application:
19/002,139 →
Publication:
US US20260186812A1
Performance Transceiver
Application:
18/754,502 →
Publication:
US US20260005721A1
Modular Multipliers using Hybrid Reduction Techniques
Application:
18/897,297 →
Publication:
US US20250013431A1
Methods and Apparatus for Waveguide Alignment Between Optical Components
Application:
18/615,740 →
Publication:
US US20250298199A1
Data Transfer Using Coherent Doorbell Updates
Application:
18/756,818 →
Publication:
US US20240354248A1
Axi-To-Memory Ip Protocol Bridge
Application:
18/777,991 →
Publication:
US US20240370395A1
Content-Addressable Memory based Nondeterministic Finite Automata Accelerator
Application:
18/756,368 →
Publication:
US US20240345953A1
Systems and Methods for Efficient Convergence for Time Servo
Application:
19/000,974 →
Publication:
US US20250132967A1
Communication Apparatus, Control Method, and Computer-Readable Storage Medium
Application:
19/266,326 →
Publication:
US US20250344234A1
Reduced Leakage Tracking Switch Circuit
Application:
19/309,462 →
Publication:
US US20250392307A1
Transceiver Delay Calibration Systems and Methods
Application:
19/233,726 →
Publication:
US US20250310007A1
Systems And Methods For Debugging Cryptographic Modules
Application:
18/236,737 →
Publication:
US US20230393197A1
Techniques For Storing States Of Signals In Configurable Storage Circuits
Application:
18/397,673 →
Publication:
US US20240137026A1
Techniques for Infield Testing of Cryptographic Circuitry
Application:
18/106,244 →
Publication:
US US20240264231A1
Programmable Logic Device-Based Software-Defined Vector Engines
Application:
18/398,688 →
Publication:
US US20240152357A1
Equalizer Circuits And Methods For Transmitting Data Using Three-Level Signaling
Application:
19/089,967 →
Publication:
US US20250226853A1
High Performance Systems And Methods For Modular Multiplication
Application:
17/952,085 →
Publication:
US US20230026331A1
Techniques For Configurable Selection Between Hard Logic And Configurable Logic Gates
Application:
18/530,665 →
Publication:
US US20250192785A1
Complex Number Matrix Multiplication Processors, Methods, Systems, and Instructions
Application:
17/985,869 →
Publication:
US US20240160443A1
Multi-Protocol Input/Output (I/O) Communication
Application:
19/093,962 →
Publication:
US US20250225102A1
High-Throughput Low-Power Decoder
Application:
18/394,282 →
Publication:
US US20250211255A1
Cross-Coupled Power Multiplexing in High Voltage Applications
Application:
18/140,481 →
Publication:
US US20240364333A1
Face-To-Face Through-Silicon via Multi-Chip Semiconductor Apparatus with Redistribution Layer Packaging and Methods of Assembling Same
Application:
18/901,904 →
Publication:
US US20250022774A1
Techniques For Synchronous Accesses To Storage Circuits
Application:
18/084,158 →
Publication:
US US20230118912A1
Vector Processor Architectures
Application:
19/071,690 →
Publication:
US US20250238232A1
Systems And Methods For Generating Redacted Circuit Designs For Integrated Circuits
Application:
18/120,857 →
Publication:
US US20240311537A1
Multichip Package with Protocol-Configurable Data Paths
Application:
18/830,452 →
Publication:
US US20240427721A1
Block Floating Point Support
Application:
18/401,432 →
Publication:
US US20250208833A1
Micro-Network-On-Chip and Microsector Infrastructure
Application:
18/912,321 →
Publication:
US US20250036591A1
Flexible Instruction Set Architecture Supporting Varying Frequencies
Application:
19/244,789 →
Publication:
US US20250315079A1
Interface Bridge Between Integrated Circuit Die
Application:
18/900,364 →
Publication:
US US20250021506A1
Systems And Methods For Coupling Integrated Circuit Dies
Application:
18/206,840 →
Publication:
US US20240096810A1
Device, Method and System for Communicating Between Networked Agents via a Credit Management Bus
Application:
18/375,069 →
Publication:
US US20250110813A1
On-Cavity Photonic Integrated Circuit (Ocpic) to Achieve the Most Undercut Real Estate for Effective Thermal Tuning
Chained Command Architecture for Packet Processing
Techniques For Power Management In Compute Circuits
Network Systems And Methods For Word Based Arbitration Of Data
Embedded Arithmetic Blocks for Structured ASICs
Programmable Device Implementing Fixed and Floating Point Functionality in a Mixed Architecture
Constraints-Based Phased Array Calibration
Application:
16/913,868 →
Publication:
US US20200328789A1
Dynamic Provisioning of Pcie Devices at Run Time for Bare Metal Servers
Application:
17/559,427 →
Publication:
US US20220156211A1
Crossbar Circuits And Methods For External Communication With Logic In Integrated Circuits
Application:
17/853,772 →
Publication:
US US20220334979A1
Techniques For Sharing Memory Interface Circuits Between Integrated Circuit Dies
Application:
17/852,093 →
Publication:
US US20220334983A1
Dynamic Power Load Line by Configuration
Application:
17/856,776 →
Publication:
US US20220335190A1
Secure Boot Using Parallelization
Application:
18/147,784 →
Publication:
US US20240220626A1
Undercut Architectures for Improved Thermal Efficiency in Photonic Integrated Circuit (Pic) Architectures
Application:
18/189,911 →
Publication:
US US20240319457A1
Methods and Apparatus to Perform Low Overhead Sparsity Acceleration Logic for Multi-Precision Dataflow in Deep Neural Network Accelerators
Application:
17/709,337 →
Publication:
US US20220292366A1
Floating-Point Dynamic Range Expansion
Application:
18/754,921 →
Publication:
US US20240345804A1
Efficient Logic Blocks Architectures for Dense Mapping of Multipliers
Application:
18/473,870 →
Publication:
US US20240028295A1
Link Monitoring and Indication of Potential Link Failure
Circuit Design Visibility in Integrated Circuit Devices
Detection of Lte Enb and Ue Emitters Using Signal Processing Algorithms for Feature Recognition
Hybrid Multipy-Accumulation Operation with Compressed Weights
Application:
18/184,101 →
Publication:
US US20230229917A1
Processor Controlled Programmable Logic Device Modification
Fabric Memory Network-On-Chip
Application:
17/711,840 →
Publication:
US US20220221986A1
Inter-Die Communication of Programmable Logic Devices
Application:
18/478,003 →
Publication:
US US20240028544A1
Embedded Programmable Logic Device for Acceleration in Deep Learning-Focused Processors
Application:
17/484,439 →
Publication:
US US20220044123A1
Workload-Dependent Integrated Circuit Operation Based on Power Headroom
Integrated Circuit Device with Separate Die for Programmable Fabric and Programmable Fabric Support Circuitry
Application:
18/300,330 →
Publication:
US US20230253965A1
Systems And Methods For Circuit Design Dependent Programmable Maximum Junction Temperatures
Methods and Apparatus to Derive and Verify Virtual Physical Unclonable Keys
Floating-Point Decomposition Circuitry with Dynamic Precision
Systems And Methods For Load Balancing Memory Traffic
Deep Trench Capacitor Bridge for Multi-Chip Package
Application:
17/889,395 →
Publication:
US US20240063148A1
Systems and Methods for Low Power Modes for Programmable Logic Devices
Programmable Logic Circuits Using Lookup Tables (LUTs) Augmented with Configurable Logic Gates
Application:
18/756,645 →
Publication:
US US20240354480A1
Configurable Voltage Regulator
Application:
19/000,748 →
Publication:
US US20250130606A1
Systems and Methods for Simulating Hardened Circuitry via Virtual Interface
Application:
18/991,091 →
Publication:
US US20250124203A1
Multi-Level Signaling Linearity Feedback and Adjustment
Application:
19/002,449 →
Publication:
US US20250126001A1
Techniques For Providing Supply Current To Dies In A System Using An Inductor
Application:
18/677,712 →
Publication:
US US20240312905A1
Security Techniques for Shared Use of Accelerators
Application:
18/621,950 →
Publication:
US US20240241973A1
Configurable Fpga Access Control
Application:
18/756,788 →
Publication:
US US20240345985A1
Heterogenous Acceleration of Workloads using xPUs and FPGAs
Application:
18/990,883 →
Publication:
US US20250117358A1
Mapping Memory Addresses from Single Instruction, Multiple Thread (Simt) Processor to Memory Banks of Banked Memory in Different Ways During Runtime
Application:
18/822,039 →
Publication:
US US20260064428A1
Dynamic Credit Allocation with Closed-Loop Feedback Integration
Application:
19/251,084 →
Publication:
US US20250321917A1
Systems and Methods for Dynamically Adjusting Clock Skips to Mitigate Voltage Droop
Application:
19/092,839 →
Publication:
US US20250272463A1
Techniques For Providing Electrostatic Discharge Protection Using An Off-Chip Capacitor
Application:
19/249,721 →
Publication:
US US20250323495A1
Systems And Methods For Generating A Temperature Dependent Supply Voltage
Instructions for Floating Point Multiplication and Addition and Conversion Employing Variable Precision
Application:
18/194,327 →
Publication:
US US20240329991A1
Techniques For Configuring Repeater Circuits In Active Interconnection Devices
Application:
18/537,571 →
Publication:
US US20240111703A1
Network-On-Chip (Noc) with Flexible Data Width
Application:
19/029,471 →
Publication:
US US20250167786A1
Single Instruction, Multiple Thread (Simt) Processors, Methods, Systems, and Instructions
Application:
18/213,257 →
Publication:
US US20230333857A1
Reconfigurable Deframer for Optical Communications
Application:
18/397,214 →
Publication:
US US20250219739A1
Extended Floating-Point Range Processors, Methods, Systems, and Instructions
Application:
18/210,635 →
Publication:
US US20240419444A1
Fast Fourier Transform (FFT) Based Digital Signal Processing (DSP) Engine
Application:
19/174,879 →
Publication:
US US20250240020A1
Technologies for an Optical Interposer with Actuator Beams
Application:
18/479,012 →
Publication:
US US20250110294A1
Photonics Integrated Circuit Embedded in a Glass Substrate and Optically Coupled with a Photonic Wire Bond
Application:
18/236,216 →
Publication:
US US20250067925A1
First-In First-Out Buffer with Lookahead Performance Booster
Application:
18/912,326 →
Publication:
US US20250036157A1
Floating-Point Decomposition Circuitry with Dynamic Precision
Application:
19/002,480 →
Publication:
US US20250123801A1
Programmable Integrated Circuit Underlay
Application:
18/796,279 →
Publication:
US US20240394448A1
Fast Fpga Compilation Through Bitstream Stitching
Application:
18/338,236 →
Publication:
US US20230333826A1
Optical Interconnects for Flexible Calibration of an Optical Transceiver in a Free-Space Optical Communication System
Application:
19/207,426 →
Publication:
US US20260005758A1
Systems And Methods For Securing Input/Output Data
Application:
18/089,398 →
Publication:
US US20230126961A1
Network Functions Virtualization Platforms with Function Chaining Capabilities
Logic Fabric Based on Microsector Infrastructure
Application:
18/795,146 →
Publication:
US US20240396556A1
Interrupt Handling by Migrating Interrupts Between Processing Cores
Application:
19/176,114 →
Publication:
US US20250238259A1
Shared Non-Blocking Crossbar Buffer Circuits And Methods
Techniques For Increasing Activation Sparsity In Artificial Neural Networks
Systems And Methods For Tracking Synthesis Optimizations For Circuit Designs
Mitigation of Side Channel Attacks on Platform Interconnects Using Endpoint Hardware Based Detection, Synchronization and Re-Keying
Application:
17/954,157 →
Publication:
US US20240106644A1
Scalable 2.5D Interface Circuitry for Data Communication Operations
Systems And Methods With Auxiliary Control Boards Having Interface Devices
Signal Lines for Semiconductor Devices
Application:
18/542,457 →
Publication:
US US20250201693A1
Techniques For Capturing Signals From Logic Circuits At A Logic Analyzer
Application:
18/122,238 →
Publication:
US US20230213581A1
Systems and Methods to Reduce Voltage Guardband
Application:
19/205,824 →
Publication:
US US20250271826A1
Systems and Methods for Programmable Fabric Design Compilation
Package Substrate with Power Delivery Network
Clock Gating and Clock Scaling Based on Runtime Application Task Graph Information
Application:
17/692,405 →
Publication:
US US20220197613A1
Embedded Multi-Die Interconnect Bridge with Improved Power Delivery
Application:
17/581,751 →
Publication:
US US20220149029A1
Controlled Transition Between Configuration Mode and User Mode to Reduce Current-Resistance Voltage Drop
Systems and Methods for Modular Disaggregated Integrated Circuit Systems
Application:
17/856,643 →
Publication:
US US20220337251A1
Reconfigurable Inlet Power Feed and Integrated Circuit Power
Circuits And Methods For Sub-Bank Sharing Of External Interfaces
Circuits And Methods For Receiving Data Signals Having Different Common-Mode Voltages
Application:
18/432,538 →
Publication:
US US20240178801A1
Techniques For Providing Shielding Between Inductors Using Guard Rings
Application:
18/956,735 →
Publication:
US US20250087577A1
Enhanced Adaptive Logic Circuitry with Improved Function Coverage and Packing Ability
Application:
18/756,634 →
Publication:
US US20240348252A1
Two-Dimensional Actuator Beam for Adjustable Optical Coupling on Photonic Integrated Circuit Structures
Application:
18/609,860 →
Publication:
US US20250298188A1
Filtering with Tensor Structures
Application:
18/899,127 →
Publication:
US US20250021305A1
Methods and Apparatus to Improve Performance of a Computing Device Implementing an Exponential Function
Application:
18/933,924 →
Publication:
US US20250060941A1
Electronic Devices Having Oval Power Delivery Pads
Application:
18/680,058 →
Publication:
US US20240321716A1
Signal Transfer with a Bridge and Hybrid Bumps
Application:
18/757,046 →
Publication:
US US20240346224A1
Power on Reset (Por) Signaling in Multi-Die Architecture
Application:
19/000,610 →
Publication:
US US20260180572A1
Techniques For Using Machine Learning To Test Integrated Circuit Dies
Application:
19/238,094 →
Publication:
US US20250315583A1
Systems And Methods For Communication Between Integrated Circuits Using Networks-On-Chip
Application:
19/093,815 →
Publication:
US US20250225092A1
Backside Metallization for FPGA Resources
Application:
17/957,210 →
Publication:
US US20230024515A1
Method and Apparatus to Enable CPU Host-Unaware Dynamic FPGA Reconfiguration
Modular Compilation Flows for a Programmable Logic Device
Application:
18/191,785 →
Publication:
US US20230237231A1
System-In-Package Network Processors
Application:
19/081,217 →
Publication:
US US20250219964A1
Asymmetrical Memory Circuits And Methods
Application:
18/241,217 →
Publication:
US US20230410897A1
Systems and Methods for Decomposed Digital Filter
Application:
18/145,002 →
Publication:
US US20230128025A1
Fast CAD Compilation Through Coarse Macro Lowering
Application:
18/475,512 →
Publication:
US US20240020449A1
Modular Periphery Tile for Integrated Circuit Device
Application:
18/951,492 →
Publication:
US US20250077753A1
Power Management using Voltage Islands on Programmable Logic Devices
Application:
19/219,865 →
Publication:
US US20250286555A1
Rank-Based Dot Product Circuitry
Application:
19/002,465 →
Publication:
US US20250123804A1
Package Io Escape Routing on a Disaggregated Shoreline
Application:
17/957,204 →
Publication:
US US20230028475A1
Architecture and Testing for an Integrated Circuit Package
Application:
18/217,200 →
Publication:
US US20230341463A1
Digital Signal Processing Circuitry with Multiple Precisions and Dataflows
Application:
18/373,878 →
Publication:
US US20240118870A1
Techniques For Managing Packet Scheduling From Queue Circuits
Application:
18/538,386 →
Publication:
US US20240113985A1
Multiplier with a new Partial Product Generation Method
Application:
18/399,595 →
Publication:
US US20250217109A1
Systems and Methods for Supporting Both Pulse Amplitude Modulation and Quadrature Amplitude Modulation
Application:
19/232,499 →
Publication:
US US20250310173A1
Data Clearing Attestation
Application:
18/390,958 →
Publication:
US US20240121079A1
Systems And Methods For Verification Of Data Erasure
Application:
18/196,112 →
Publication:
US US20240380607A1
Host Managed Memory Shared by Multiple Host Systems in a High Availability System
Application:
18/071,923 →
Publication:
US US20240176740A1
Simt Processor with Storage Having Sets of Storage Locations Corresponding to Different Threads of a Parallel Thread Group to Store Data Elements Output from Corresponding Sets of Registers of a Register File
Application:
18/966,083 →
Publication:
US US20250094378A1
Source Synchronous Partition of an SDRAM Controller Subsystem
Application:
18/085,528 →
Publication:
US US20230123826A1
Field Replaceable Fan Assemblies for Peripheral Processing Units and Related Systems and Methods
Application:
17/957,698 →
Publication:
US US20230016098A1
3D Convolutional Neural Network (CNN) Implementation on Systolic Array-Based FPGA Overlay CNN Accelerator
Application:
18/129,341 →
Publication:
US US20230237014A1
Systems And Methods For Generating Placements For Circuit Designs Using Pyramidal Flows
Systems And Methods For Electronically Scanned Array Antennas
Application:
18/792,306 →
Publication:
US US20240396579A1
Processing Unit, Software module, Methods and Program Codes
Application:
17/643,854 →
Publication:
US US20220129252A1
Systems And Methods For Accessing Memory Devices Using Virtual Memory Ranks
Heterogeneous Timing Closure For Clock-Skew Scheduling or Time Borrowing
Application:
17/856,804 →
Publication:
US US20220334609A1
Programmable Fabric-Based Instruction Set Architecture for a Processor
Field-Configurable Optical Switch Implementations Within Multi-Chip Packages
Application:
17/359,374 →
Publication:
US US20220413216A1
Multiple Channel Direct Access Memory-Based Configuration System
Reticle Stitching to Achieve High-Capacity Integrated Circuit
Channel Sizing for Inter-Kernel Communication
Application:
17/328,878 →
Publication:
US US20210349702A1
Programmable Memory Controller Circuits And Methods
Exception Handler Based Error Correction for Processors
Application:
19/315,435 →
Publication:
US US20250390384A1
Scalable Network-on-Chip for High-Bandwidth Memory
Integrated Circuit Package with Electro-Optical Interconnect Circuitry
Application:
18/795,148 →
Publication:
US US20240418951A1
Three-Dimensional Columnar Input-Output (IO) Circuitry for Integrated Circuit Device
Segmented Row Repair for Programmable Logic Devices
Systems and Methods for Sparsity Operations in a Specialized Processing Block
Application:
17/485,123 →
Publication:
US US20220012012A1
Freeze And Clear Logic Circuits And Methods For Integrated Circuits
Driver Circuits And Methods For Supplying Leakage Current To Loads
Application:
18/989,641 →
Publication:
US US20250123647A1
Summation and Floating Point Conversion of Tensor Results
Application:
18/900,192 →
Publication:
US US20250045017A1
Low Static Phase Error Charge Pump for PLL Without Calibration
Application:
18/990,950 →
Publication:
US US20250150082A1
Boundary Scan Power Up Voltage Level Configuration
Application:
19/002,100 →
Publication:
US US20250123328A1
Dynamic Provisioning of Precision Time Protocol (PTP) Enabled Ports in Multiclock Architecture
Application:
18/990,998 →
Publication:
US US20250150190A1
Mixed-Radix Multiplier Circuit
Application:
18/622,048 →
Publication:
US US20250306854A1
Techniques For Testing Input And Output Buffer Circuits Using A Test Bus
Application:
18/736,308 →
Publication:
US US20240319262A1
Segmented Boundary Scan Chain Testing
Application:
18/757,740 →
Publication:
US US20240353490A1
Techniques For Transferring Heat From Electronic Devices Using Heatsinks
Application:
18/678,439 →
Publication:
US US20240321670A1
Flash Adc Comparator Interpolation
Application:
18/616,729 →
Publication:
US US20250309910A1
Detection of Short Resets of an Electronic Device
Application:
18/620,757 →
Publication:
US US20240241994A1
Adaptive Decision Feedback Equalization Tuning
Application:
18/617,467 →
Publication:
US US20240235902A1
Circuits And Methods For Tampering Detection
Application:
18/610,682 →
Publication:
US US20240220671A1
Systems and Methods for Packet Processing in Programmable Logic Devices
Application:
18/620,712 →
Publication:
US US20250310263A1
Techniques For Coarse Grained And Fine Grained Configurations Of Configurable Logic Circuits
Application:
18/584,339 →
Publication:
US US20240193331A1
Dynamic Fabric Quiescence
Application:
18/615,994 →
Publication:
US US20240231461A1
Techniques For Reconfiguring Lookup Tables Using Memory During User Mode
Application:
18/936,210 →
Publication:
US US20250061257A1
Key Store System For Controlling Access To Keys
Application:
19/245,108 →
Publication:
US US20250315538A1
Methods and Apparatus for Profile-Guided Optimization of Integrated Circuits
Application:
19/303,140 →
Publication:
US US20250371235A1
Techniques For Routing Between A Network-On-Chip And Multiplexer Circuits In A Central Region Of An Integrated Circuit
Application:
19/092,814 →
Publication:
US US20250226818A1
Double Bump Design for Multiple Purpose IO Connections
Application:
19/002,453 →
Publication:
US US20250125296A1
Temperature Gradient Control for Internal Regulated Supply
Application:
18/398,760 →
Publication:
US US20240184319A1
Method and System for on-the-Fly Graph Partitioning Resource Utilization
Application:
19/325,372 →
Publication:
US US20250383937A1
Flushing Cache Lines Involving Persistent Memory
Photonic Integrated Circuit Edge Coupling and Fiber Attach Unit Attachment Stress Relief
Application:
18/326,458 →
Publication:
US US20240402442A1
Extended Floating-Point Range Addition and Multiplication
Application:
18/210,630 →
Publication:
US US20230367547A1
Current Control Systems And Methods For Communications Between Devices
Application:
18/372,696 →
Publication:
US US20250104745A1
Techniques For Compiling High-Level Inline Code
Application:
18/077,170 →
Publication:
US US20230116554A1
Techniques For Accessing Memory Circuits
Application:
18/085,819 →
Publication:
US US20230131938A1
Data Compression in Integrated Device Network
Application:
17/957,380 →
Publication:
US US20230037575A1
Iterative Multiplicative Reduction Circuit
Application:
18/122,656 →
Publication:
US US20230273770A1
Protection System for Gate Drivers
Application:
18/398,966 →
Publication:
US US20240128963A1
Circuit Systems And Methods Using Spacer Dies
Application:
18/070,361 →
Publication:
US US20230100829A1
Multi Programable-Die Module
Application:
18/210,847 →
Publication:
US US20240145434A1
Selective Use of Different Advanced Interface Bus with Electronic Chips
Application:
19/216,402 →
Publication:
US US20250285985A1
Virtual Platforms of Integrated Circuit Designs
Application:
18/481,935 →
Publication:
US US20240037305A1
Techniques For Replacing Logic Circuits In Modules With Configurable Circuits
Techniques For Controlling Access To Provisioning Integrated Circuits
Application:
18/369,612 →
Publication:
US US20240005044A1
Apparatus and Method for Graceful Degradation of Redundant Processing
Application:
18/217,349 →
Publication:
US US20250004892A1
Software-Defined Synthesizable Testbench
Application:
17/970,557 →
Publication:
US US20230052788A1
Methods And Apparatus For Selectively Extracting And Loading Register States
Application:
19/261,909 →
Publication:
US US20250335019A1
Die-to-Die Interconnect Architecture for Hardware-Agnostic Modeling
Application:
17/956,372 →
Publication:
US US20230042718A1
Circuits And Methods For Multi-Layered Networks
Application:
18/478,755 →
Publication:
US US20240031308A1
Timing Model for Chip-to-Chip Connection in a Package
Application:
18/375,299 →
Publication:
US US20240028815A1
TUNABLE EDGE-COUPLED INTERFACE FOR SILICON PHOTONIC INTEGRATED CIRCUITS (PICs) AND METHOD FOR MAKING SAME
Application:
18/362,033 →
Publication:
US US20250044537A1
Embedded Faraday Rotators and Components for Increasing Bandwidth and/or Reducing Fiber Count in Photonics Multi Chip Packages
Application:
19/244,646 →
Publication:
US US20250317206A1
Accurate Timestamp Measurements for a Single Step Precision Time Protocol
Application:
18/399,600 →
Publication:
US US20250220004A1
Precoding During Link Establishment
Application:
18/143,034 →
Publication:
US US20240235906A1
Coherent Reception of on/Off Keying and Pulse Position Modulations
Application:
18/397,271 →
Publication:
US US20250219740A1
Stacked Die Network Interface Controller Circuitry
Application:
18/757,034 →
Publication:
US US20240347514A1
Systems and Methods for Communicating Encrypted Time-Related Data
Temperature Sensor to Achieve Thermal Stabilization of Micro-Ring Resonator (Mrr) in an Open Cavity Photonic Integrated Circuit (Ocpic)
Graph Memory Engine
Application:
19/185,014 →
Publication:
US US20250272242A1
Antenna Hopping for Specific Absorption Rate (Sar) Reduction
Systems and Methods for Structured Mixed-Precision in a Specialized Processing Block
Fabric Memory Network-On-Chip Extension to ALM Registers and LUTRAM
Techniques For Reduction Of Degradation In Channels Caused By Bias Temperature Instability
Systems and Methods for Reducing Congestion on Network-On-Chip
Programmable Routing Bridge
Application:
17/856,768 →
Publication:
US US20220337248A1
Homogenous Die Stacking With Increased Element Density
Multichip Package Staircase Cavities
Application:
17/485,295 →
Publication:
US US20230101340A1
Incremental Just-in-Time (Jit) Performance Refinement for Programmable Logic Device Offload
Circuit Implementation on Processing Circuitry
Power Allocation using Multiple Voltage Domains for Programmable Logic Devices
Debug Trace Microsectors
Application:
19/072,997 →
Publication:
US US20250208209A1
Method and System for Efficient Partitioning and Construction of Graphs for Scalable High-Performance Search Applications
Application:
18/520,358 →
Publication:
US US20240104136A1
Techniques to Share Memory Across Nodes in a System
Application:
18/127,324 →
Publication:
US US20230236995A1
Embedded Multi-Die Interconnect Bridge with Improved Power Delivery
Application:
17/716,928 →
Publication:
US US20220230993A1
Clocking Architecture for a Multi-Die Package
Application:
17/711,784 →
Publication:
US US20220224342A1
Higher-Voltage-Protected Transmission Gate to Prevent Unbalanced Aging Stress on Differential Receiver Input
Application:
18/620,740 →
Publication:
US US20240243740A1
Circuits And Methods For Preventing Row Hammer Attacks To Memory Circuits
Application:
18/789,413 →
Publication:
US US20240386102A1
IC Device Resource Sharing
Application:
18/756,964 →
Publication:
US US20240345884A1
Modular Fabric Architecture in Fpga Products
Application:
18/757,170 →
Publication:
US US20240348253A1
Programmable Multi-Protocol Adapter for Integrated Circuit
Application:
18/900,217 →
Publication:
US US20250023959A1
Techniques For Masking Mutable Fields During Transmission And Receipt Of Packets
Application:
18/608,233 →
Publication:
US US20250291958A1
Systems And Methods For Configuring Signal Paths In An Interposer Between Integrated Circuits
Application:
18/601,665 →
Publication:
US US20240213985A1
Modular Heatsink for Integrated Circuit Package
Application:
18/677,669 →
Publication:
US US20250372474A1
Machine Learning Control of Clock Drift
Application:
18/756,925 →
Publication:
US US20240345161A1
Circuits And Methods For Memory Built-In-Self-Tests
Application:
18/809,696 →
Publication:
US US20240412799A1
Techniques For Testing Leakage Current In Input And Output Circuits
Application:
18/800,444 →
Publication:
US US20240402245A1
Circuits And Methods For Converting A Wideband Digital Signal Into A Wideband Analog Signal
Application:
18/987,557 →
Publication:
US US20250119155A1
Systems and Methods for Protocol Decoders in a Signal Analysis System Using Hardware Description Language
Application:
18/990,983 →
Publication:
US US20260178805A1
Distributed Attestation in Heterogenous Computing Clusters
Application:
19/299,604 →
Publication:
US US20250373449A1
Dynamically Mixed Precision Machine Learning Systems and Methods
Application:
19/094,251 →
Publication:
US US20250224920A1
Transposed Digital Filter Circuitry
Application:
18/988,356 →
Publication:
US US20260180557A1
Multiple PCIe Interfaces with Deadlock Avoidance
Application:
19/251,075 →
Publication:
US US20250321916A1
Digital Signal Processing (DSP) Block with Systolic Filter Support Circuitry
Application:
18/988,363 →
Publication:
US US20260178277A1
Active Interposers For Migration Of Packages
Application:
18/392,162 →
Publication:
US US20240162189A1
Configurable Semiconductor Package Capacitors and Method
Application:
18/129,443 →
Publication:
US US20240332222A1
Flexible Scaffold Chiplet Interconnect Systems and Methods
Application:
19/251,044 →
Publication:
US US20250322127A1
Programmable Logic Device Embedded Block Power Control
Application:
19/002,400 →
Publication:
US US20260187331A1
Micro Through-Silicon via for Transistor Density Scaling
Application:
19/248,022 →
Publication:
US US20250385161A1
Power Delivery Systems and Methods with a Single Power Rail
Application:
19/251,122 →
Publication:
US US20250323162A1
Lut-Free Hardware Based Softmax Accelerator
Application:
19/055,819 →
Publication:
US US20250190523A1
Neural Network Accelerator Performing Operation with Mixed-Format Weights
Application:
18/931,973 →
Publication:
US US20250060940A1
Multi-Purpose Interface for Configuration Data and User Fabric Data
Distributed Attestation in Heterogenous Computing Clusters
Recessed Vertical Interconnects for Device Miniaturization
Circuits And Methods For Routing Crossbars With Programmable Vias
Circuits And Methods For Configurable Scan Chains
Power on Reset Circuitry for Manufacturability and Security Using a Fuse
Patent:
8,026,746 →
Application:
12/784,075 →
Stacked Semiconductor Substrates
Patent:
8,294,252 →
Application:
12/431,625 →
Programmable Logic Device Having Logic Elements with Dedicated Hardware to Configure Look Up Tables as Registers
Patent:
8,601,424 →
Application:
12/893,904 →
Embedding Identification Information on Programmable Devices
Patent:
7,472,369 →
Application:
10/861,990 →
Volatile Memory Elements with Boosted Output Voltages for Programmable Logic Device Integrated Circuits
Method and Apparatus for Placement and Routing of Partial Reconfiguration Modules
Circuit Distribution to Multiple Integrated Circuits
Patent:
8,000,106 →
Application:
11/969,373 →
Method to Digitize Analog Signals in a System Utilizing Dynamic Analog Test Multiplexer for Diagnostics
Apparatus and Method for Input/Output Module That Optimizes Frequency Performance in a Circuit
Apparatus for All-Digital Serializer-De-Serializer and Associated Methods
Timing Control in a Specialized Processing Block
Patent:
8,020,027 →
Application:
12/049,560 →
Hardware True Random Number Generator in Integrated Circuit with Tamper Detection
Patent:
8,321,773 →
Application:
12/262,666 →
Techniques and Apparatus to Validate an Integrated Circuit Design
Patent:
8,661,379 →
Application:
13/803,595 →
Economical, Scalable Transceiver Jitter Test
Peak Suppression of Multi-Carrier Signal with Different Modulation
Forward Error Correction Codec
Programmable Logic Device with Specialized Functional Block
Patent:
7,698,358 →
Application:
10/746,448 →
Local Constraints for Motion Matching
One-Time Programmable Memories for Key Storage
Patent:
7,818,584 →
Application:
11/042,937 →
Controllable Pre-Distortion for Transmitter Circuitry on Programmable Logic Device Integrated Circuits
Patent:
7,432,741 →
Application:
11/641,990 →
Method and Apparatus for Facilitating an Adaptive Electronic Design Automation Tool
Patent:
7,509,618 →
Application:
10/844,285 →
Flip Chip Overmold Package
Method and Apparatus for Parameterizing Hardware Description Language Code in a System Level Design Environment
Patent:
8,176,450 →
Application:
12/806,710 →
Integrated Circuits with Adjustable Memory Element Power Supplies
Patent:
7,463,057 →
Application:
11/394,033 →
Configurable Emphasis for High-Speed Transmitter Driver Circuitry
Patent:
7,924,046 →
Application:
12/776,871 →
Duty Cycle Correction Circuitry
Patent:
7,999,588 →
Application:
12/551,434 →
Micromagnetic Device and Method of Forming the Same
Hardware and Software Debugging
Patent:
8,214,701 →
Application:
12/425,958 →
Ic with Deskewing Circuits
Interactive Design Optimization Techniques and Interface
Patent:
8,196,085 →
Application:
12/690,059 →
Programmable Vias for Structured Asics
Method of Forming a Micromagnetic Device
Method, Device and System for Multi Field Classification in a Data Communications Network
Techniques for Adjusting Level Shifted Signals
Patent:
7,884,644 →
Application:
12/709,492 →
System for Adapting Device Standards After Manufacture
Integrated Circuit Well Isolation Structures
Patent:
7,902,611 →
Application:
11/998,016 →
Low-Power Routing Multiplexers
Controllable Storage Elements for an IC
Central Alignment Circutry for High-Speed Serial Receiver Circuits
Integrated Current Replicator and Method of Operating the Same
System Reset Controller Replacing Individual Asynchronous Resets
Systems and Methods for Providing Memory Controllers with Scheduler Bypassing Capabilities
Patent:
8,930,641 →
Application:
13/160,384 →
Circuitry and Techniques for Updating Configuration Data in an Integrated Circuit
Method and System for Efficiently Transitioning a Communication Circuit from a Low-Power State
Patent:
8,788,862 →
Application:
13/175,745 →
Programmable Device Implementing Fixed and Floating Point Functionality in a Mixed Architecture
Patent:
9,507,565 →
Application:
14/180,664 →
Multi-Channel Encryption and Authentication
Patent:
10,237,066 →
Application:
14/247,597 →
Asymmetric Power Flow Controller for a Power Converter and Method of Operating the Same
Low Leakage Finfet
Patent:
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Application:
14/677,448 →
Integrated Circuits with Optical Flow Computation Circuitry
Patent:
9,819,841 →
Application:
14/689,792 →
METHODS AND APPARATUS FOR GENERATING Short Length Patterns that Induce Inter-Symbol Interference
Patent:
9,177,087 →
Application:
13/289,785 →
Latency Computation Circuitry
Patent:
9,268,888 →
Application:
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Semiconductor Device Including Alternating Source and Drain Regions, and Respective Source and Drain Metallic Strips
Programmable Integrated Circuits with Multiplexer and Register Pipelining Circuitry
Patent:
10,489,116 →
Application:
14/326,828 →
Hash Generation Circuitry and Methods for Multi-Channel, Multi-Lane Encryption and Authentication
Patent:
9,519,807 →
Application:
14/513,519 →
Systems and Methods for Sharing Multiple Lock-Detect Circuitries Or Multiple Phase Locked Loop Blocks
Patent:
10,361,708 →
Application:
15/277,783 →
Techniques and Circuitry for Configuring and Calibrating an Integrated Circuit
Techniques for Aligning and Reducing Skew in Serial Data Signals
Data Compression Profiler for Configuration of Compression
Systems and Methods for Using Memory Commands
Configurable Storage Elements
Processing System and Method Including Data Compression Api
Programmable Logic Device with a Self-Power Down Mechanism
Programmable Circuit Having Multiple Sectors
Method and Apparatus for Performing Timing Closure Analysis When Performing Register Retiming
Patent:
9,275,184 →
Application:
14/159,905 →
Methods for Operating Configurable Storage and Processing Blocks at Double and Single Data Rates
Patent:
9,385,724 →
Application:
14/045,658 →
Transformable Logic and Routing Structures for Datapath Optimization
Adaptive Refresh Scheduling for Memory
Patent:
9,595,312 →
Application:
15/086,884 →
Method and Apparatus for Improving System Operation by Replacing Components for Performing Division During Design Compilation
Variable Precision Floating-Point Multiplier
Selectable Reconfiguration for Dynamically Reconfigurable Ip Cores
Patent:
10,831,960 →
Application:
16/190,091 →
Integrated Circuits with Machine Learning Extensions
Network-On-Chip for Inter-Die and Intra-Die Communication in Modularized Integrated Circuit Devices
Die to Die Interconnect Structure for Modularized Integrated Circuit Devices
Configuration of a Programmable Device
Methods and Apparatus for Providing Deterministic Latency for Communications Interfaces
Parameterizable Method for Simulating Pll Behavior
Patent:
9,628,095 →
Application:
13/604,577 →
Variable Precision Floating-Point Adder and Subtractor
Method and Apparatus for Performing Timing Analysis on Calibrated Paths
Patent:
9,684,742 →
Application:
12/803,097 →
Enhanced Ball Grid Array
Patent:
9,462,691 →
Application:
14/158,660 →
Method and Apparatus for Data Re-Packing for Link Optimization
Patent:
10,505,837 →
Application:
13/938,179 →
Methods for Incremental Circuit Physical Synthesis
Patent:
10,936,772 →
Application:
15/233,855 →
Circuits and Methods for Generating a Clock Enable Signal Using a Shift Register
Patent:
9,812,216 →
Application:
15/197,442 →
Methods for Operating Configurable Storage and Processing Blocks at Double and Single Data Rates
Patent:
9,768,783 →
Application:
15/183,457 →
Differential Input Buffer Circuits and Methods
Patent:
9,647,663 →
Application:
15/193,518 →
Data Compression and Decompression Using Simd Instructions
Memory Arbitration Circuitry
Placement Based Arithmetic Operator Selection
Patent:
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Application:
14/278,675 →
Methods and Systems for Performing Signal Activity Extraction
Patent:
9,026,980 →
Application:
14/199,922 →
Transceiver Power Distribution Network
Patent:
8,937,258 →
Application:
14/473,884 →
Method And Circuit For Scalable Cross Point Switching Using 3-D Die Stacking
Systems and Methods for Reducing Static and Total Power Consumption in Programmable Logic Device Architectures
Patent:
8,806,249 →
Application:
12/206,240 →
Apparatus and Methods for Optimization of Integrated Circuits
Patent:
8,949,763 →
Application:
12/242,365 →
Input-Output Buffer Circuitry with Increased Drive Strength
Patent:
8,975,928 →
Application:
13/871,931 →
Method and Apparatus for Relocating Design Modules While Preserving Timing Closure
Patent:
9,195,793 →
Application:
14/154,623 →
Coreless Organic Substrate
Patent:
9,648,728 →
Application:
14/601,973 →
Input-Output Buffer Circuit with a Gate Bias Generator
Patent:
9,385,718 →
Application:
14/058,117 →
Integrated Circuit Device with Embedded Programmable Logic
Patent:
9,589,612 →
Application:
14/602,131 →
Memory Access System
Patent:
8,874,866 →
Application:
12/693,288 →
Specialized Processing Block with Fixed- and Floating-Point Structures
Patent:
9,098,332 →
Application:
13/486,255 →
High-K Dielectric Device and Process
Patent:
8,835,265 →
Application:
13/525,864 →
Reduced Matrix Reed-Solomon Encoding
Patent:
8,898,551 →
Application:
13/530,683 →
Methods for Implementing Arithmetic Functions with User-Defined Input and Output Formats
Patent:
9,811,503 →
Application:
14/608,113 →
Method and Apparatus for Performing Time Domain Jitter Modeling
Patent:
8,904,331 →
Application:
13/537,115 →
Apparatus and Methods for Multiple-Channel Direct Memory Access
Patent:
9,684,615 →
Application:
14/592,385 →
Input Voltage Clamp with Signal Splitting and Cross-Over Capabilities
Patent:
9,571,075 →
Application:
14/624,234 →
Techniques For Power Control Of Circuit Blocks
Method and Apparatus for Satisfying Operating Conditions in a System Design Using an Electronic Design Automation Tool
Patent:
9,922,150 →
Application:
14/538,666 →
Security Variable Scrambling
Patent:
9,722,778 →
Application:
15/219,103 →
Interface Architecture for Master-to-Master and Slave-to-Master Communication
Patent:
10,579,552 →
Application:
15/429,018 →
Methods and Apparatus for Using Load and Store Addresses to Resolve Memory Dependencies
On-Device Bitstream Validation
Method and Apparatus for Performing Synthesis for Field Programmable Gate Array Embedded Feature Placement
Techniques For Preventing Voltage Tampering Of Security Control Circuits
Programmable Logic Device with Fine-Grained Disaggregation
Clock Grid For Integrated Circuit
Patent:
9,843,332 →
Application:
15/496,549 →
Asymmetric Power Flow Controller for a Power Converter and Method of Operating the Same
Maintaining Reconfigurable Partitions in a Programmable Device
Inter-Die Communication of Programmable Logic Devices
Method Apparatus for High-Level Programs with General Control Flow
Active Interposer for Localized Programmable Integrated Circuit Reconfiguration
Apparatus to Synchronize Clocks of Configurable Integrated Circuit Dies Through an Interconnect Bridge
Transmitter Circuitry with N-Type Pull-Up Transistor and Low Output Voltage Swing
Apparatus For Flexible Electronic Interfaces And Associated Methods
Management of Cache Use Requests Sent to Remote Cache Devices
Method and Apparatus for Automatic Hierarchical Design Partitioning
High-Speed Serial Data Signal Receiver Circuitry
Data Storage For Accelerating Functions
Methods and Apparatus for Continuous Time Linear Equalizer Tuning Using Decision Feedback Equalizer Adaptation Engine
Patent:
10,305,703 →
Application:
15/390,216 →
Decomposable Forward Error Correction
Dynamic Deep Learning Processor Architecture
Methods for Memory Interface Calibration
Memory Controller Architecture with Improved Memory Scheduling Efficiency
Multi-Level Signaling for on-Package Chip-to-Chip Interconnect Through Silicon Bridge
Interleaved T-Coil Structure and a Method of Manufacturing the T-Coil Structure
Patent:
9,502,168 →
Application:
14/081,970 →
Method and Apparatus for Performing Profile Guided Optimization for High-Level Synthesis
Patent:
10,558,437 →
Application:
13/746,518 →
Partial Reconfiguration Control Interface for Integrated Circuits
Patent:
9,584,130 →
Application:
15/164,503 →
Method and Apparatus for Supporting Temporal Virtualization on a Target Device
Methods for Determining Resistive-Capacitive Component Design Targets for Radio-Frequency Circuitry
Patent:
10,223,483 →
Application:
15/390,322 →
Semiconductor Device Including Gate Drivers Around a Periphery Thereof
Debugging an Optimized Design Implemented in a Device with a Pre-Optimized Design Simulation
Patent:
9,298,865 →
Application:
14/220,926 →
Method and Apparatus for Automatically Configuring Memory Size
Patent:
8,813,018 →
Application:
13/646,559 →
Programmable Device Using Fixed and Configurable Logic to Implement Floating-Point Rounding
Patent:
9,348,795 →
Application:
13/934,421 →
Circuitry and Methods for Implementing Galois-Field Reduction
Patent:
9,619,207 →
Application:
14/524,526 →
Apparatus and Method to Reduce Memory Subsystem Power Dynamically
Patent:
10,416,910 →
Application:
15/270,515 →
Methods and Apparatus for Reducing Spatial Overlap Between Routing Wires
Patent:
9,564,394 →
Application:
14/546,320 →
Configurable Storage Blocks with Embedded First-in First-Out and Delay Line Circuitry
Patent:
9,824,024 →
Application:
14/530,576 →
Fixed-Point and Floating-Point Optimization
Patent:
9,696,991 →
Application:
13/727,835 →
Secure Boot Using a Field Programmable Gate Array (Fpga)
Patent:
9,600,291 →
Application:
14/201,016 →
Power and Die Size Optimization in Finfets
Patent:
9,397,095 →
Application:
14/222,630 →
Sample Rate Converter
Patent:
9,331,703 →
Application:
14/482,998 →
Systems and Methods for Reducing Power Supply Noise or Jitter
Patent:
9,748,934 →
Application:
14/616,406 →
Method and Apparatus for Placing and Routing Partial Reconfiguration Modules
Systems and Methods for Interfacing Between Hard Logic and Soft Logic in a Hybrid Integrated Device
Micro-Granular Delay Testing of Configurable Ics
Method and apparatus for error-correction in and processing of GFP-T superblocks
Methods and Apparatus for Reordering Data Signals in Fast Fourier Transform Systems
Patent:
8,812,819 →
Application:
13/212,377 →
Systems and Methods for Configuring an Sopc Without a Need to Use an External Memory
Calculation of Trigonometric Functions in an Integrated Circuit Device
Memory Elements with Stacked Pull-Up Devices
Memory Controller Architecture with Improved Memory Scheduling Efficiency
Patent:
9,911,477 →
Application:
14/256,721 →
Run-Time Recovery of Malformed Interconnect Response
Patent:
9,141,488 →
Application:
14/100,841 →
Integrated Circuit with Bonding Circuits for Bonding Memory Controllers
Patent:
9,558,131 →
Application:
13/164,426 →
Method and Apparatus for Decomposing Functions in a Configurable Ic
Intellectual Property (Ip) Blocks with Customizable Configuration Status Register (Csr) Circuitry
Patent:
10,546,087 →
Application:
15/082,870 →
Input-Output Circuitry for Integrated Circuits
Patent:
9,106,230 →
Application:
13/828,467 →
Zero-Offset Sampling for Clock Duty Cycle Correction
Design for Test Techniques and Circuitry
Patent:
9,021,323 →
Application:
13/046,620 →
Power Delivery for Embedded Interconnect Bridge Devices and Methods
Backchannel Transmission Adaptation
Patent:
9,923,738 →
Application:
15/273,310 →
Techniques for Determining Inductances
Patent:
10,361,554 →
Application:
15/278,013 →
Integrated Circuit (Ic) Clocking Techniques
Patent:
8,755,480 →
Application:
13/341,722 →
Specialized Processing Block for Implementing Floating-Point Multiplier with Subnormal Operation Support
Patent:
8,996,600 →
Application:
13/566,256 →
Clock Structure with Calibration Circuitry
Patent:
8,816,743 →
Application:
13/749,450 →
Adaptable Programs Using Partial Reconfiguration
Patent:
9,100,012 →
Application:
13/715,716 →
Timing Analysis with End-of-Life Pessimism Removal
Patent:
8,977,998 →
Application:
13/773,468 →
Fast Fourier Transform (FFT) Based Digital Signal Processing (DSP) Engine
Micro Through-Silicon via for Transistor Density Scaling
Folded Integer Multiplication for Field-Programmable Gate Arrays
Device, Method and System to Determine Calibration Information with a Shared Ring Oscillator Circuit
On-Die Termination (Odt) Circuit Configurable with via Layer to Support Multiple Standards
Fiber Shuffle Embedded Optical Connector
Data and Clock Synchronization and Variation Compensation Apparatus and Method
Programmable Integrated Circuit Underlay
Modular Periphery Tile for Integrated Circuit Device
Modular Periphery Tile for Integrated Circuit Device
Denormalization in Multi-Precision Floating-Point Arithmetic Circuitry
Magnetically Decoupled Inductor Structures
Patent:
9,941,201 →
Application:
15/013,885 →
Electronic Systems For Integrated Circuits And Voltage Regulators
Variable Precision Floating-Point Multiplier
Stacked Die Network Interface Controller Circuitry
Configurable Clock Macro Circuits And Methods
Dynamically Scalable Timing and Power Models for Programmable Logic Devices
Graph Memory Engine
Face-To-Face Through-Silicon via Multi-Chip Semiconductor Apparatus with Redistribution Layer Packaging and Methods of Assembling Same
Scalable 2.5D Interface Circuitry
Soft Network-on-Chip Overlay Through a Partial Reconfiguration Region
At-Speed Burst Sampling for User Registers
High Precision Decomposable Dsp Entity
Interrupt Handling by Migrating Interrupts Between Processing Cores
Adaptive Cyclic Delay Line for Fractional-N Pll
Methods for Optimizing Circuit Performance via Configurable Clock Skews
FPGA Specialist Processing Block for Machine Learning
Microcontroller Controlled or Direct Mode Controlled Network-Fabric on a Structured Asic
Patent:
8,677,306 →
Application:
13/649,551 →
Flexible Physical Function and Virtual Function Mapping
Apparatus and Methods for High-Speed Interpolator-Based Clock and Data Recovery
Patent:
8,831,157 →
Application:
14/040,203 →
System and Method for Creating a Scalable Monolithic Packet Processing Engine
Methods and Apparatus for High-Speed Serial Interface Link Assist
Patent:
10,417,169 →
Application:
15/264,293 →
Programmable Integrated Circuits with Decoupling Capacitor Circuitry
Patent:
9,329,608 →
Application:
14/212,599 →
Hybrid Architecture for Signal Processing and Signal Processing Accelerator
Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure
Method and Apparatus for Performing Register Retiming in the Presence of False Path Timing Analysis Exceptions
Patent:
9,971,858 →
Application:
14/627,220 →
Driver for Network Timing Systems
Method and Apparatus for Performing Fast Incremental Resynthesis
Patent:
9,147,023 →
Application:
14/228,378 →
Method and System for Dynamic Table Line Encoding
Patent:
8,638,245 →
Application:
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Pam-N Jitter/Noise Decomposition Analysis
Patent:
10,020,967 →
Application:
15/443,791 →
Systems and Methods for Detecting and Mitigating Programmable Logic Device Tampering
Floating-Point Adder Circuitry
Adder Circuitry for Very Large Integers
ESD Protection Circuit
Patent:
8,912,605 →
Application:
13/538,508 →
Multi-Rate Transceiver Circuitry
Pam-N Jitter/Noise Decomposition Analysis
Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure
Distributed Multi-Die Protocol Application Interface
Method and Apparatus for Implementing a System-Level Design Tool for Design Planning and Architecture Exploration
Short Link Efficient Interconnect Circuitry
Method and Apparatus for Deskewing Data Transmissions
Distributed Multi-Die Protocol Application Interface
Memory Interface with Hybrid Error Detection Circuitry for Modular Designs
Patent:
9,342,402 →
Application:
14/166,337 →
Method and Apparatus for Performing Efficient Incremental Compilation
Patent:
10,073,941 →
Application:
14/466,563 →
Compression Using Mu-Law Approximation
Patent:
9,762,285 →
Application:
15/259,369 →
Innovative Interconnect Design for Package Architecture to Improve Latency
Serial Memory Interface Circuitry for Programmable Integrated Circuits
Method and Apparatus for Implementing Configurable Streaming Networks
Patent:
10,224,934 →
Application:
15/352,406 →
Integrated Circuit Device Configuration Methods Adapted to Account for Retiming
Sharing a Jtag Interface Among Multiple Partitions
Patent:
10,101,387 →
Application:
15/429,008 →
Block Floating Point Compression of Signal Data
Dynamic Bias Circuit
Method and Apparatus for Performing Rewind Structural Verification of Retimed Circuits Driven by a Plurality of Clocks
Scaleable Look-Up Table Based Memory
Patent:
9,548,103 →
Application:
14/806,962 →
Seemingly Monolithic Interface Between Separate Integrated Circuit Die
Compensation Network Using an on-Die Compensation Inductor
Patent:
8,368,174 →
Application:
12/833,888 →
Method and Apparatus for Performing Register Retiming in the Presence of Timing Analysis Exceptions
Patent:
9,710,591 →
Application:
14/627,191 →
Transceiver Parameter Solution Space Visualization to Reduce Bit Error Rate
Reference Clock Architecture for Integrated Circuit Device
Patent:
9,479,181 →
Application:
14/339,722 →
Innovated Technique to Reduce Memory Interface Write Mode Ssn in Fpga
Patent:
7,492,185 →
Application:
11/956,182 →
Fabric Die to Fabric Die Interconnect for Modularized Integrated Circuit Devices
Method and Apparatus for Simultaneous Switching Noise Optimization
Patent:
8,296,704 →
Application:
12/833,797 →
Scalable 2.5D Interface Circuitry
Patent:
9,971,733 →
Application:
14/960,175 →
Application-Based Dynamic Heterogeneous Many-Core Systems and Methods
System and Method for Reducing Reconfiguration Power Usage
Device with Logic Circuitry Supporting Quaternary Addition
Processor for a Base Station Control Unit
Patent:
8,897,784 →
Application:
13/852,715 →
Power Gated Lookup Table Circuitry
Method and Apparatus for Securing Programming Data of a Programmable Device
Innovative Interconnect Design for Package Architecture to Improve Latency
Method and Apparatus for Verifying Structural Correctness in Retimed Circuits
Multi-threaded software-programmable framework for high-performance scalable and modular datapath designs
Patent:
8,761,188 →
Application:
12/150,889 →
Methods and Apparatus for Programming an Integrated Circuit Using a Configuration Memory Module
Method and Apparatus for Performing Rewind Structural Verification of Retimed Circuits Driven by a Plurality of Clocks
Integrating Multiple Fpga Designs by Merging Configuration Settings
Patent:
8,635,571 →
Application:
13/656,361 →
Methods and Apparatus for Sequencing Multiply-Accumulate Operations
Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure
Scalable Interconnect Modules with Flexible Channel Bonding
Repairable Io in an Integrated Circuit
Patent:
8,174,284 →
Application:
13/014,990 →
Systems and Methods for Detecting and Mitigating Programmable Logic Device Tampering
Scalable Network-on-Chip for High-Bandwidth Memory
Programmable Control Block for Dual Port Sram Application
Pipelined Systolic Finite Impulse Response Filter
Patent:
9,379,687 →
Application:
14/193,477 →
Transceiver Parameter Solution Space Visualization to Reduce Bit Error Rate
Patent:
9,727,402 →
Application:
14/616,139 →
Circuit Design Technique for Dqs Enable/Disable Calibration
Patent:
9,158,873 →
Application:
14/312,325 →
Configurable Ic with Large Carry Chains
Reference Clock Architecture for Integrated Circuit Device
Patent:
9,979,403 →
Application:
15/295,856 →
Multiple Gate Semiconductor Devices and Their Applications
Patent:
9,166,052 →
Application:
14/576,610 →
Power Converter with Power Switch Operable in Controlled Current Mode
Reconfigurable Logic Block
Power Converter Employing a Micromagnetic Device
Configuration Context Switcher with a Latch
Systems and Methods for Predictive Scheduling and Rate Limiting
Dense Digital Arithmetic Circuitry Utilization for Fixed-Point Machine Learning
Hardware Accelerator Template and Design Framework for Implementing Recurrent Neural Networks
Systems and Methods for Region-Based Error Detection and Management in Integrated Circuits
Apparatuses to Resolve Roles for Dual Role Serial Bus Devices
Methods and Apparatus for Profile-Guided Optimization of Integrated Circuits
Systems and Methods for Implementing Learned Parameter Systems on a Programmable Integrated Circuit
Distributed Programmable Delay Lines in a Clock Tree
Universal Transceiver Container
Enumerated Per Device Addressability for Memory Subsystems
Spintronic devices, duplexers, transceivers and telecommunication devices
Implementing Device Models for Virtual Machines with Reconfigurable Hardware
Multi-Purpose Interface for Configuration Data and User Fabric Data
High Radix Subset Code Multiplier Architecture
Apparatus and Methods for Low-Jitter Transceiver Clocking
Patent:
8,406,258 →
Application:
12/752,984 →
Multi-Channel Communication Circuitry for Programmable Logic Device Integrated Circuits and the Like
Apparatus and Methods for on-Die Instrumentation
Patent:
8,837,571 →
Application:
13/958,395 →
Apparatus and Methods for Serial Interfaces with Shared Datapaths
Patent:
8,571,059 →
Application:
13/194,536 →
Apparatus and Method for Polarity Tap Control
Patent:
9,094,239 →
Application:
13/632,263 →
Programmable Logic Device with Serial Interconnect
Module Having a Stacked Magnetic Device and Semiconductor Device and Method of Forming the Same
Very Low Voltage Reference Circuit
Configuration Context Switcher with a Clocked Storage Element
System and Method of Providing a Memory Hierarchy
Patent:
7,930,666 →
Application:
11/609,875 →
Configurable Ic's with Configurable Logic Circuits That Perform Adder and/or Subtractor Operations
Multi-Protocol Channel-Aggregated Configurable Transceiver in an Integrated Circuit
Zeroization Verification of Integrated Circuit
Patent:
8,437,200 →
Application:
13/022,144 →
Stiffener for Flip Chip Bga Package
Patent:
7,459,782 →
Application:
11/244,953 →
Data Interleaving and Deinterleaving Involving Concatenation of Words Read from Storage
Patent:
7,954,015 →
Application:
12/315,772 →
Buffer Circuitry with Multiport Memory Cells
Patent:
8,611,173 →
Application:
13/310,501 →
Apparatus and Associated Methods for Generating Reference Signals
Patent:
8,125,362 →
Application:
12/334,219 →
Multi-Phase Interpolators and Related Methods
Patent:
8,294,500 →
Application:
12/621,493 →
Methods and Apparatus for Providing a Scalable Motion Estimation/Compensation Assist Function Within an Array Processor
Configurable Ic Having a Routing Fabric with Storage Elements
Interactive Configuration of Connectivity in Schematic Diagram of Integrated Circuit Design
Patent:
8,205,183 →
Application:
12/562,889 →
Integrated Circuits with Clearable Memory Elements
Patent:
7,911,826 →
Application:
12/057,343 →
Dynamic Test Signal Routing Controller
Patent:
8,407,541 →
Application:
12/818,985 →
Integrated Circuits with Interconnect Selection Circuitry
Patent:
8,542,032 →
Application:
13/345,436 →
Method and Apparatus for Parameterizing Hardware Description Language Code in a System Level Design Environment
Patent:
7,793,248 →
Application:
11/286,814 →
Low Ripple Charge Pump
Patent:
8,013,666 →
Application:
12/534,066 →
Method of Forming a Power Module with a Magnetic Device Having a Conductive Clip
Strict-Sense Minimal Spanning Switch Non-Blocking Architecture
Fpga Configuration Data Scrambling Using Input Multiplexers
Patent:
8,650,409 →
Application:
10/942,151 →
On-Chip Data Signal Eye Monitoring Circuitry and Methods
Patent:
8,111,784 →
Application:
12/082,483 →
Logic Structures and Methods Supporting Pipelined Multi-Operand Adders
Patent:
8,510,357 →
Application:
13/755,929 →
Method and Apparatus for Reducing Synthesis Runtime
Patent:
7,415,693 →
Application:
10/851,355 →
Techniques for Boundary Scan Testing Using Transmitters and Receivers
Integrated Circuit with Delay Selecting Input Selection Circuitry
Common Clock Path Pessimism Analysis for Circuit Designs Using Clock Tree Networks
Patent:
7,926,019 →
Application:
12/039,918 →
Adaptive Equalization Using Data Level Detection
Patent:
8,175,143 →
Application:
12/037,284 →
Multi-Protocol Low Latency Automatic Speed Negotiation Architecture for an Embedded High Speed Serial Interface in a Programmable Logic Device
Patent:
7,684,477 →
Application:
11/490,406 →
Data Width Scaler Circuitry
Patent:
8,193,953 →
Application:
12/780,478 →
Pulse Width Control Circuitry
Patent:
8,253,463 →
Application:
12/721,488 →
Programmable Device Configuration Methods Adapted to Account for Retiming
Patent:
8,677,298 →
Application:
13/733,982 →
Platform Interface Layer and Protocol for Accelerators
Embedded Network on Chip Accessible to Programmable Logic Fabric of Programmable Logic Device in Multi-Dimensional Die Systems
Apparatus and Methods for Calibrating Analog Circuitry in an Integrated Circuit
Hybrid Architecture for Signal Processing and Signal Processing Accelerator
Efficient Integrated Circuits Configuration Data Mangement
Heat Spreading in Molded Semiconductor Packages
Electrostatic Discharge Protection Circuitry
Patent:
8,878,296 →
Application:
12/910,416 →
Face-To-Face Through-Silicon via Multi-Chip Semiconductor Apparatus with Redistribution Layer Packaging and Methods of Assembling Same
Systems and Methods for Integrating Power and Thermal Management in an Integrated Circuit
Signal Flow Control Through Clock Signal Rate Adjustments
Methods for Testing Network Circuitry
Method and Apparatus For Supporting A Unified Debug Environment
Integrated Circuit Power Systems with Machine Learning Capabilities
On-Die Aging Measurements for Dynamic Timing Modeling
Apparatus for Flexible Electronic Interfaces and Associated Methods
Reduced Latency Multiplier Circuitry for Very Large Numbers
Hybrid Programmable Many-Core Device with on-Chip Interconnect
Integrated Circuits Having Memory with Flexible Input-Output Circuits
Bumpless Wafer Level Fan-Out Package
Wide Band Deterministic Interface
Patent:
9,042,431 →
Application:
12/391,712 →
Systems and Methods for Reducing Leakage Current in Memory Arrays
Patent:
8,861,283 →
Application:
13/605,428 →
Power Converter for a Memory Module
HIGH-SPEED PERIPHERAL COMPONENT INTERCONNECT (PCIe) INPUT-OUTPUT DEVICES WITH RECEIVE BUFFER MANAGEMENT CIRCUITRY
Patent:
9,552,323 →
Application:
13/936,063 →
Integrated Circuit Device with Field Programmable Optical Array
Patent:
9,608,728 →
Application:
14/163,780 →
Seemingly Monolithic Interface Between Separate Integrated Circuit Die
Integrated Circuit Calibration System Using General Purpose Processors
Patent:
9,778,312 →
Application:
14/055,459 →
Flexible High Speed Forward Error Correction (Fec) Physical Medium Attachment (Pma) and Physical Coding Sublayer (Pcs) Connection System
Patent:
9,235,540 →
Application:
13/781,839 →
Fluid Routing Devices and Methods for Cooling Integrated Circuit Packages
Method and Apparatus for Protecting, Optimizing, and Reporting Synchronizers
Patent:
9,342,640 →
Application:
14/229,358 →
Multi-Access Memory System and a Method to Manufacture the System
Patent:
9,679,871 →
Application:
14/263,904 →
Multi-Standard Peak Canceling Circuitry
Patent:
9,485,129 →
Application:
14/325,184 →
Stacked Leadframe Packages
Patent:
9,601,419 →
Application:
14/298,230 →
Methods and Apparatus for Performing Reed-Solomon Encoding
Methods and Apparatus for Implementing Feedback Loops
Patent:
9,660,624 →
Application:
14/221,819 →
Strain-Enhanced Transistors with Adjustable Layouts
Patent:
9,634,094 →
Application:
14/181,447 →
On-Die Input Reference Voltage with Self-Calibrating Duty Cycle Correction
Patent:
9,711,189 →
Application:
13/209,307 →
Area-Efficient Dynamically-Configurable Memory Controller
Patent:
9,229,888 →
Application:
13/562,124 →
Finfet with Improved Seu Performance
Patent:
9,543,382 →
Application:
14/663,237 →
Partial Reconfiguration Using Configuration Transaction Layer Packets
Patent:
9,257,987 →
Application:
14/594,927 →
Incremental Register Retiming of an Integrated Circuit Design
Dual Interlocked Cell (Dice) Storage Element with Reduced Charge Sharing
Patent:
9,344,067 →
Application:
13/951,780 →
System and Methods for Debug Connectivity Discovery
Patent:
9,404,968 →
Application:
14/063,957 →
Error Detection and Correction Circuitry
Patent:
9,600,366 →
Application:
14/632,461 →
Integrated Circuit with Continuously Adaptive Equalization Circuitry
Patent:
9,705,708 →
Application:
15/170,751 →
Methods and Apparatus for Performing Partial Reconfiguration in a Pipeline-Based Network Topology
Systems And Methods For Configuring A Secure Computing Environment On An Integrated Circuit
Patent:
10,372,946 →
Application:
15/295,785 →
Retiming with Programmable Power-Up States
Patent:
10,255,404 →
Application:
15/195,843 →
N-Depth Asynchronous Fifo Including a Collection of 1-Depth Fifo Cells
Configuration via High Speed Serial Link
Method and Apparatus for Securing Configuration Scan Chains of a Programmable Device
Deterministic Fifo Buffer
Methods and Structures for Handling Integrated Circuits
Clock and Data Recovery Circuitry with Auto-Speed Negotiation and Other Possible Features
Method and Apparatus for Die Testing
Patent:
8,952,713 →
Application:
13/369,224 →
Systems and Methods for Handling Interrupts During Software Design Simulation
Patent:
9,075,639 →
Application:
13/658,057 →
Clocking for Pipelined Routing
Packet Communication Testing Apparatus and Associated Methods
Patent:
8,850,300 →
Application:
12/908,529 →
Calculation of Trigonometric Functions in an Integrated Circuit Device
Techniques for Generating a Single Configuration File for Multiple Partial Reconfiguration Regions
Patent:
8,997,033 →
Application:
14/197,918 →
HIGH-K DIELECTRIC dEVICE AND pROCESS
Patent:
9,166,045 →
Application:
14/473,953 →
Flexible Input Structure for Arithmetic Processing Block
Patent:
10,003,341 →
Application:
15/201,815 →
Pipelined Cascaded Digital Signal Processing Structures and Methods
Systems and Methods for a Low Hold-Time Sequential Input Stage
Design and Manufacture of Interconnects for Integration of Multiple Integrated Circuits
Patent:
10,541,205 →
Application:
15/432,823 →
Micro Through-Silicon via for Transistor Density Scaling
Rom Segmented Bitline Circuit
Hardened Programmable Devices
Silicon-Glass Hybrid Interposer Circuitry
Multichip Module with Reroutable Inter-Die Communication
Methods for Delaying Register Reset for Retimed Circuits
Patent:
10,169,518 →
Application:
15/342,286 →
Hybrid Programmable Many-Core Device with on-Chip Interconnect
Multiple Alternate Configurations for an Integrated Circuit Device
Patent:
9,548,740 →
Application:
14/020,978 →
Clock Control Circuitry and Methods of Utilizing the Clock Control Circuitry
Patent:
9,075,112 →
Application:
14/108,063 →
Specialized Processing Blocks with Fixed-Point and Floating-Point Structures
Patent:
10,127,013 →
Application:
15/390,358 →
Dynamic Clock-Data Phase Alignment in a Source Synchronous Interface Circuit
Digital Monobit Dithering Circuit
Patent:
9,998,275 →
Application:
14/694,785 →
Multiple-Precision Processing Block in a Programmable Integrated Circuit Device
Patent:
9,189,200 →
Application:
13/829,729 →
Programmable Interposer Circuitry
Patent:
9,106,229 →
Application:
13/829,965 →
Clock Data Recovery Circuitry with Programmable Clock Phase Selection
Patent:
9,112,655 →
Application:
13/954,751 →
Integrated Circuit Package with a Universal Lead Frame
Patent:
9,337,240 →
Application:
12/819,141 →
Methods for Performing Register Retiming Operations into Synchronization Regions Interposed Between Circuits Associated with Different Clock Domains
Configurable Register Circuitry for Error Detection and Recovery
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9,583,218 →
Application:
14/252,752 →
Method and Apparatus for Performing Automatic Decoupling Capacitor Selection for Power Distribution Networks
Patent:
9,582,628 →
Application:
14/095,184 →
Double-Precision Floating-Point Operation
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10,007,487 →
Application:
15/199,626 →
Methods and Apparatus for Multiple-Stage Ctle Adaptation
Patent:
9,172,566 →
Application:
14/057,945 →
Programmable Device Using Fixed and Configurable Logic to Implement Recursive Trees
Patent:
9,600,278 →
Application:
13/941,847 →
Integrated Circuits with Improved Memory Controllers
Patent:
9,805,775 →
Application:
14/075,940 →
Bitstream Verification on Embedded Processor-Fpga Platform
Patent:
8,924,907 →
Application:
14/089,596 →
Methods and Apparatus for Transceiver Power Noise Reduction
Patent:
8,923,417 →
Application:
13/349,418 →
M/A for Performing Automatic Latency Optimization on System Designs for Implementation on Programmable Hardware
Patent:
8,918,748 →
Application:
13/593,665 →
Method and System for Reducing the Effect of Component Aging
Patent:
9,058,436 →
Application:
13/682,730 →
Methods and Structures for Compensating and Tracking Process, Voltage and Temperature Variations
Patent:
9,077,514 →
Application:
14/166,252 →
Techniques For Noise Reduction During Calibration
Patent:
9,203,352 →
Application:
13/952,412 →
Smart Diagnosis of Integrated Circuits Including Ip Cores with Encrypted Simulation Models
Pulse-Width Modulation Voltage Identification Interface
Method and Apparatus for Using Programmable Logic Circuitry to Test on-Chip Analog-to-Digital Converter
Patent:
9,874,607 →
Application:
15/079,672 →
Method and Apparatus for Performing Late Binding of Control Status Registers in a Design Compilation Flow
Patent:
9,355,198 →
Application:
14/108,070 →
Method and Apparatus for Performing Automatic Data Compression Algorithm Selection During High-Level Compilation
Patent:
10,474,441 →
Application:
13/760,516 →
Digital Signal Processing Circuitry with Redundancy and Ability to Support Larger Multipliers
Patent:
8,886,696 →
Application:
12/380,853 →
Adaptations for Partial Response Summation Node Embedded Fpga Transceiver
Patent:
9,264,276 →
Application:
14/541,251 →
Methods and Apparatus for Performing Product Series Operations in Multiplier Accumulator Blocks
Apparatus and Method for Common Mode Tracking in DFE Adaptation
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8,831,084 →
Application:
13/609,173 →
Channel Sizing for Inter-Kernel Communication
Level-Sensitive Two-Phase Single-Wire Latch Controllers Without Contention
Patent:
9,385,717 →
Application:
14/291,487 →
CRC Circuits with Extended Cycles
Patent:
9,639,416 →
Application:
13/831,466 →
Parallel Crc Calculation for Multiple Packets Without Requiring a Shifter
Patent:
10,171,108 →
Application:
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Optimizing Ic Performance Using Sequential Timing
Ic and a Method of Testing a Transceiver of the Ic
Patent:
8,887,016 →
Application:
13/372,354 →
Integrated Circuit Package with Inter-Die Thermal Spreader Layers
Patent:
8,941,233 →
Application:
13/402,632 →
Methods and Circuitry for Performing Parallel Error Checking
Patent:
8,918,706 →
Application:
13/677,181 →
Programmable High-Speed Voltage-Mode Differential Driver
Low Power Advertising Mode for Sequential Image Presentation
Method and Apparatus for Reducing Constraints During Rewind Structural Verification of Retimed Circuits
Detection and Disposition of Commands Methods and Apparatuses
Microelectronics Assembly Including Top and Bottom Packages in Stacked Configuration with Shared Cooling
Circuit Design Instrumentation for State Visualization
Techniques For Reducing The Effects Of Aging In Logic Circuits
Toggle Rate Reduction in High Level Programming Implementations
Configuration via High Speed Serial Link
Methods and Apparatus for Regulating the Supply Voltage of an Integrated Circuit
Adjusting a Continuous Time Linear Equalization-Based Receiver
Systems and Methods for Aligning Received Data
Generating a Timestamp
Digital Signal Processing Blocks with Embedded Arithmetic Circuits
Patent:
10,101,966 →
Application:
15/478,056 →
High Performance Fpga Addition
Patent:
10,340,920 →
Application:
16/147,098 →
Method and Apparatuses for Optimizing Power Management on an Integrated Circuit Device
Patent:
9,735,778 →
Application:
14/464,588 →
Reconfigurable Equalization Architecture for High-Speed Receivers
Patent:
9,025,654 →
Application:
14/028,071 →
High-Speed Data Communications Architecture
Patent:
9,048,889 →
Application:
14/075,861 →
Method and Apparatus for Operating Finite-State Machines in Configurable Storage Circuits
Patent:
9,218,862 →
Application:
14/251,423 →
Using Fpga Partial Reconfiguration for Codec Applications
Patent:
9,191,617 →
Application:
14/139,286 →
Negative Bit Line Driver Circuitry
Patent:
9,256,266 →
Application:
13/289,953 →
Method and Apparatus for Linear Function Processing in Pipelined Storage Circuits
Patent:
9,804,843 →
Application:
14/478,335 →
Methods and Apparatus for Performing Floating Point Operations
Patent:
9,904,512 →
Application:
13/907,134 →
Equalizer Circuitry Including Both Inductor Based and Non-Inductor Based Equalizer Stages
Patent:
8,816,745 →
Application:
13/316,361 →
Techniques For Transferring Time Information Between Clock Domains
Patent:
9,001,951 →
Application:
13/329,188 →
Systems and Methods for Encoding and Decoding Data
Patent:
9,047,203 →
Application:
13/722,750 →
Workgroup Handling in Pipelined Circuits
Patent:
9,135,087 →
Application:
13/727,813 →
Protocol Error Monitoring on an Interface Between Hard Logic and Soft Logic
Patent:
9,170,911 →
Application:
13/938,014 →
Integrated Circuit Package with Embedded Passive Structures
Patent:
9,673,173 →
Application:
14/808,743 →
Speculative Circuit Design Component Graphical User Interface
Patent:
9,529,952 →
Application:
14/704,721 →
Apparatus for Configurable Eleronic Circuitry and Associated Methods
Patent:
8,680,886 →
Application:
13/105,976 →
Low-Skew Channel Bonding Using Oversampling
Patent:
9,772,649 →
Application:
14/724,166 →
Startup Circuit
Patent:
9,035,641 →
Application:
13/154,149 →
Integrated Circuits with Improved Register Circuitry
Patent:
9,660,650 →
Application:
14/209,503 →
Mask Set for Fabricating Integrated Circuits and Method of Fabricating Integrated Circuits
Patent:
9,401,281 →
Application:
14/281,515 →
Serdes Circuit Ctle Adaptation Using Isi Metering
Interface Discovery Between Partitions of a Programmable Logic Device
Network-On-Chip (Noc) with Flexible Data Width
Embedded Dual-Sided Interconnect Bridges for Integrated-Circuit Packages
Systems and Methods for Aligning Received Data
Techniques for Using Scan Storage Circuits
Patent:
9,588,176 →
Application:
14/610,341 →
Active Interposer for Localized Programmable Integrated Circuit Reconfiguration
Device Under Test Board with Offset Connection to Host Board
Methods and Apparatus for Selectively Extracting and Loading Register States
Computing System for Mitigating Execution Drift
Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure
Converting Multiple Light Signals into and Out of a Single Wavelength with Multiple Polarizations to Increase Optical Bandwidth
Methods for Memory Interface Calibration
Patent:
9,911,506 →
Application:
15/416,347 →
Techniques For Clock Signal Transmission In Integrated Circuits And Interposers
Circuit and Method for Link Verification by HDCP Receiver
Error Correcting Code Circuitry Compatible with Multi-Width Interfaces
Systems And Methods For Transmitting And Receiving Auxiliary Data
Serdes Circuit Automatic Gain Control and Convergence
Network-On-Chip for Inter-Die and Intra-Die Communication in Modularized Integrated Circuit Devices
Network Functions Virtualization Platforms with Function Chaining Capabilities
Debug Trace Microsectors
Modular Periphery Tile for Integrated Circuit Device
Wireless modem with software configurable multiple antenna ports
Methods and Apparatus to Expose a Microservice to a Software Layer
Power Management using Voltage Islands on Programmable Logic Devices
Apparatus and Method for Reusing Manufacturing Content Across Multi-Chip Packages
Electrical and Optical Interfaces at Different Heights Along an Edge of a Package to Increase Bandwidth Along the Edge
Deterministic Clustering and Packing Method for Random Logic on Programmable Integrated Circuits
Adaptive Equalization Methods and Apparatus for Programmable Logic Devices
Patent:
7,773,668 →
Application:
10/762,864 →
Coarse-Grain Programmable Routing Network for Logic Devices
Pld Package with Coordinated Rfid Tag
Controller for a Power Converter and Method of Operating the Same
Circuitry for Implementing Multi-Mode Redundancy and Arithmetic Functions
Patent:
9,362,913 →
Application:
14/499,006 →
Micro Through-Silicon via for Transistor Density Scaling
Systems and Methods for Routing Data Across Regions of an Integrated Circuit
System-In-Package Network Processors
Method and System for Calculating Timing Variations Considering Simultaneous Switching Noise
Patent:
8,825,420 →
Application:
12/690,047 →
Apparatus for Flexible Electronic Interfaces and Associated Methods
Method and Apparatus for Performing Compilation Using Multiple Design Flows
Patent:
9,122,826 →
Application:
14/052,210 →
Configuring A Programmable Device Using High-Level Language
Integrated Circuit Device Configuration Methods Adapted to Account for Retiming
Patent:
8,863,059 →
Application:
13/930,018 →
Method and Apparatus for Designing a System on Multiple Field Programmable Gate Array Device Types
Patent:
7,913,203 →
Application:
11/986,608 →
Multi-Rate Transceiver Circuitry
Patent:
9,559,834 →
Application:
14/605,871 →
High Performance Regularized Network-on-Chip Architecture
Reduced Floating-Point Precision Arithmetic Circuitry
Low-Skew Channel Bonding Using Phase-Measuring Fifo Buffer
Patent:
9,774,478 →
Application:
14/676,583 →
Low-Skew Channel Bonding Using Phase-Measuring Fifo Buffer
Continuous Parallel Cyclic Bch Decoding Architecture
Patent:
9,118,349 →
Application:
14/087,192 →
Periphery Shoreline Augmentation for Integrated Circuits
Systems and Methods for Data Transfer Over a Shared Interface
Floating-Point Dynamic Range Expansion
Circuitry for High-Bandwidth, Low-Latency Machine Learning
Multichip Package with Protocol-Configurable Data Paths
High-Speed Differential Comparator Circuitry with Accurately Adjustable Threshold
Programmable Logic Device with Improved Security
Patent:
8,812,869 →
Application:
13/557,005 →
Method and Apparatus for Implementing Layers on a Convolutional Neural Network Accelerator
Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure
Programmable Control Block for Dual Port Sram Application
Integrated Circuit (Ic) with Primary and Secondary Networks and Device Containing Such an Ic
Hierarchical Accelerator Registry for Optimal Performance Predictability in Network Function Virtualization
Patent:
9,483,291 →
Application:
14/609,306 →
Safety Features for High Level Design
Configuring a Programmable Device Using High-Level Language
Efficient Virtual I/O Address Translation
Fabric Die to Fabric Die Interconnect for Modularized Integrated Circuit Devices
Detailed Placement with Search and Repair
Method and Apparatus for Implementing a Processor Interface Block with an Electronic Design Automation Tool
Patent:
8,788,985 →
Application:
13/765,082 →
Floating-Point Adder Circuitry
Method and Apparatus for Performing Fast Incremental Physical Design Optimization
Patent:
9,569,574 →
Application:
14/200,897 →
Method and Apparatus for Performing Fast Incremental Physical Design Optimization
Patent:
10,635,772 →
Application:
15/379,747 →
Micro Through-Silicon via for Transistor Density Scaling
Method and Apparatus for Performing Multiple Stage Physical Synthesis
Patent:
8,856,702 →
Application:
13/935,633 →
Scalable 2.5D Interface Architecture
Low Latency Compact Clos Network Controller
Method of Forming a Power Module with a Magnetic Device Having a Conductive Clip
High-Speed Core Interconnect for Multi-Die Programmable Logic Devices
Method and Apparatus for Implementing Configurable Streaming Networks
Patent:
10,615,800 →
Application:
16/254,407 →
Thermal Management of Integrated Circuits
Programmable Logic Device Virtualization
Programmable Logic Device with Integrated Network-On-Chip
Method and Apparatus for Secure Provisioning of an Integrated Circuit Device
Patent:
9,729,518 →
Application:
14/255,451 →
Techniques for Protecting Security Features of Integrated Circuits
Method of Accessing Stored Information in Multi-Framed Data Transmissions.
Programmable Logic Device with Improved Security
Patent:
8,255,702 →
Application:
12/630,629 →
Multi-Channel, Multi-Lane Encryption Circuitry and Methods
Patent:
9,992,053 →
Application:
15/421,578 →
Method and Apparatus for Securing Programming Data of a Programmable Device
Methods and Apparatus for Attaching Application Specific Functions Within an Array Processor
Interface Bridge Between Integrated Circuit Die
Programmable Logic Device Virtualization
Patent:
9,503,094 →
Application:
14/875,207 →
Method and Apparatus for Securing a Programmable Device Using a Kill Switch
Programmable Logic Device with Fine-Grained Disaggregation
Memory-Mapped State Bus for Integrated Circuit
Patent:
10,372,655 →
Application:
15/463,993 →
Multichip Package with Protocol-Configurable Data Paths
Configuring a Programmable Logic Device Using a Configuration Bit Stream Without Phantom Bits
Patent:
9,130,561 →
Application:
14/533,984 →
Systems and Methods for Routing Data Across Regions of an Integrated Circuit
Partitioning Designs to Facilitate Certification
Integrated Circuit Calibration System Using General Purpose Processors
Patent:
10,495,686 →
Application:
15/683,647 →
Clock Management Block
Logic Fabric Based on Microsector Infrastructure
Interface Bridge Between Integrated Circuit Die
Digital Signature Verification Engine for Reconfigurable Circuit Devices
Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure
Shielding Structure for Transmission Lines
Block Floating Point Compression with Exponent Token Codes
Multiple Gate Semiconductor Devices and Their Applications
Patent:
8,928,382 →
Application:
13/832,619 →
Apparatus and Method for Fast-Path Memory Operations
Patent:
10,802,723 →
Application:
13/779,562 →
Cdr Control Architecture for Robust Low-Latency Exit from the Power-Saving Mode of an Embedded Cdr in a Programmable Integrated Circuit Device
Patent:
7,925,913 →
Application:
11/857,141 →
Compression of Floating-Point Data
Prioritized Error-Detection and Scheduling
System and Method for Using Fabric-Graph Flow to Determine Resource Costs
Patent:
8,789,001 →
Application:
13/831,144 →
FPGA Specialist Processing Block for Machine Learning
Apparatus and Method for Improving Lock Time
Technologies for Memory Margin Aware Reliable Software Execution
Integrated Circuit with Peek and Poke Protection Circuitry for Multi-Tenant Usage Model
Signal Detection Techniques Using Clock Data Recovery
Power Management for Pci Express
Patent:
9,965,018 →
Application:
15/269,243 →
Pipelined Systolic Finite Impulse Response Filter
Patent:
9,966,933 →
Application:
15/161,210 →
Programmable Logic Device Transceiver Architectures That Facilitate Using Various Numbers of Transceiver Channels Together
Patent:
7,812,634 →
Application:
11/726,471 →
Offset Cancellation in Equalizer Circuitry
Patent:
8,417,752 →
Application:
12/470,254 →
Clock Signal Circuitry for Multi-Channel Data Signaling
Patent:
7,812,659 →
Application:
11/432,420 →
Multi-Purpose Phase-Locked Loop for Low Cost Transceiver
Patent:
8,619,931 →
Application:
12/622,152 →
Serial Data Signal Eye Width Estimator Methods and Apparatus
Patent:
8,081,723 →
Application:
12/082,343 →
Techniques for Phase Shifting a Periodic Signal Based on a Data Signal
Patent:
8,514,995 →
Application:
13/082,336 →
Robust Time Borrowing Pulse Latches
Structure to Measure Both Interconnect Resistanc and Capacitanc
Patent:
7,900,164 →
Application:
10/759,400 →
Serial Communications Systems with Cyclic Redundancy Checking
Patent:
7,801,121 →
Application:
11/407,484 →
Performance Constraints for System Synthesis
Patent:
8,578,075 →
Application:
11/674,076 →
Automatic Test Pattern Generation System for Programmable Logic Devices
Patent:
8,516,322 →
Application:
12/568,136 →
Duty Cycle Distortion Correction Circuitry
Data Communications Circuitry with High Jitter Tolerance
Patent:
8,295,421 →
Application:
12/616,105 →
Method and Apparatus for Implementing a Parameterizable Filter Block with an Electronic Design Automation Tool
Patent:
8,499,262 →
Application:
12/807,959 →
Power Supply Circuitry for Data Signal Transceivers on Integrated Circuits
Patent:
7,639,993 →
Application:
11/295,391 →
Multiplier with Built-in Accumulator
Patent:
8,533,250 →
Application:
12/486,231 →
Avoiding Interleaver Memory Conflicts
Patent:
8,572,456 →
Application:
12/470,959 →
Calculation of Trigonometric Functions in an Integrated Circuit Device
Patent:
8,510,354 →
Application:
12/722,683 →
Dynamic Phase Alignment
Apparatus for Memory Interface Configuration
Patent:
8,223,584 →
Application:
12/431,848 →
Programmable Logic Device Integrated Circuits with Configurable Dynamic Phase Alignment Circuitry
Patent:
7,644,296 →
Application:
11/488,429 →
Stressed Transistors with Reduced Leakage
Patent:
8,138,791 →
Application:
12/694,603 →
M&A for Implementing Periphery Devices on a Programmable Circuit Using Partial Reconfiguration
Patent:
8,476,926 →
Application:
13/368,437 →
Integrated Circuit (Ic) with Primary and Secondary Networks and Device Containing Such an Ic
Dynamic Data Compression and Decompression
Patent:
8,427,347 →
Application:
13/075,656 →
Apparatus and Methods for Time-Multiplex Field-Programmable Gate Arrays with Multiple Clocks
Patent:
8,225,259 →
Application:
11/129,796 →
Systems and Methods for Flexibly Configuring a Programmable Logic Device
Patent:
8,664,975 →
Application:
13/085,679 →
Digitally Controlled Delay-Locked Loops
Patent:
7,746,134 →
Application:
11/737,116 →
Detecting Reducible Registers
Patent:
7,412,677 →
Application:
11/360,739 →
Integrated Circuit with Improved Interconnect Routing and Associated Methods
Patent:
8,629,689 →
Application:
13/475,927 →
Programmable Packet Format Converter
Patent:
7,912,085 →
Application:
11/906,204 →
Techniques for Attenuating Resonance Induced Impedance in Integrated Circuits
Patent:
8,164,916 →
Application:
11/972,550 →
Computer-Aided Design Tools and Memory Element Power Supply Circuitry for Selectively Overdriving Circuit Blocks
Patent:
8,502,558 →
Application:
13/281,135 →
Power Booster Using Peak Suppression and Pre-Distortion for Terminal Radios
Vertically Tapered Transmission Line for Optimal Signal Transition in High-Speed Multi-Layer Ball Grid Array Packages
Apparatus and Methods for Transceiver Power Adaptation
Patent:
8,611,403 →
Application:
13/446,543 →
High Speed Programming of Programmable Logic Devices
Patent:
7,795,909 →
Application:
12/103,567 →
Double Data Rate Operation in an Integrated Circuit
Patent:
8,514,994 →
Application:
12/244,568 →
Method and Apparatus for Implementing a Parameterizable Filter Block with an Electronic Design Automation Tool
Patent:
7,823,092 →
Application:
11/986,607 →
Systems and Methods for Interfacing Between Hard Logic and Soft Logic in a Hybrid Integrated Device
Method and Apparatus for Implementing Additional Registers in Field Programmable Gate Arrays to Reduce Design Size
Patent:
7,420,390 →
Application:
11/328,407 →
Pipelined Scan Structures for Testing Embedded Cores
Method and Apparatus for Performing Incremental Compilation
Patent:
7,464,362 →
Application:
11/384,962 →
Volatile Memory Elements with Soft Error Upset Immunity
Multiplier Operable to Perform a Variety of Operations
Patent:
7,720,901 →
Application:
11/441,692 →
Integrated Circuit Compilation
On-Chip Full Eye Viewer Architecture
Patent:
8,451,883 →
Application:
12/630,674 →
Controllable Storage Elements for an Ic
Resource Sharing in Decoder Architectures
Integrated Circuit with an Increased Signal Bandwidth Input/Output (I/O) Circuit
Patent:
10,110,225 →
Application:
15/341,423 →
Gating and Sampling a Data Strobe Signal Using a Shared Enable Signal
Patent:
8,929,162 →
Application:
13/531,430 →
Method and Apparatus For Automatic Hierarchical Design Partitioning
Patent:
8,832,618 →
Application:
13/553,995 →
Method and Apparatus For Performing Multi-Cadence Detection In A Motion Adaptive Video Deinterlacer
Patent:
8,836,858 →
Application:
13/679,382 →
Bidirectional Fast Fourier Transform in an Integrated Circuit Device
Patent:
9,170,985 →
Application:
13/802,505 →
Memory Error Detection Circuitry
Patent:
9,336,078 →
Application:
14/052,472 →
Adjustable Voltage Regulator Calibration Circuit
Patent:
8,898,029 →
Application:
13/046,626 →
Methods and Apparatus for Detecting Memory Bit Corruption on an Integrated Circuit
Patent:
9,582,349 →
Application:
14/464,244 →
Methods for Memory Interface Calibration
Patent:
9,558,849 →
Application:
14/060,920 →
Multilayer Quality of Service (Qos) for Network Functions Virtualization Platforms
Patent:
9,378,043 →
Application:
14/724,089 →
Techniques for Oversampling a Data Stream in an Integrated Circuit
Patent:
8,892,793 →
Application:
13/279,145 →
Integrated Circuit Applications Using Partial Reconfiguration
Patent:
9,584,129 →
Application:
14/310,902 →
Multimode Equalization Circuitry
Patent:
9,537,681 →
Application:
14/536,417 →
Systems and Methods for Performing Reverse Order Cryptographic Operations on Data Streams
Patent:
9,832,022 →
Application:
14/632,496 →
Pipelined Interconnect Circuitry with Double Data Rate Interconnections
Patent:
9,692,418 →
Application:
14/464,340 →
Protection Circuit for Decoupling a Low Voltage Circuitry from a High Voltage Circuitry
Live Migration of Hardware Accelerated Applications
Methods and Apparatus for Communicating Low-Latency Word Category Over Multi-Lane Link
Patent:
8,886,856 →
Application:
13/165,762 →
Methods and Tools for Designing Integrated Circuits with Auto-Pipelining Capabilities
Integrated Circuit Device with Stitched Interposer
Methods and Apparatus for Aligning Clock Signals on an Integrated Circuit
Method of Using a Pmos Pass Gate
Patent:
9,165,640 →
Application:
14/333,871 →
Low-Noise Voltage Regulator for Voltage-Controlled Oscillator
Patent:
9,172,384 →
Application:
14/499,768 →
Analog-To-Digital Converter Circuits and Methods
Patent:
9,154,151 →
Application:
14/579,397 →
Contactor for Reducing ESD in Integrated Circuit Testing
Patent:
9,335,343 →
Application:
13/436,285 →
Low Frequency Variation Calibration Circuitry
Patent:
10,224,908 →
Application:
13/329,089 →
Self-Tuning High Speed Transceiver For IC Wireline Channel
Patent:
9,160,405 →
Application:
12/425,216 →
Method and Apparatus For Reducing Power Spikes Caused By Clock Networks
Patent:
9,024,683 →
Application:
14/022,931 →
Guided Memory Buffer Allocation
Patent:
9,703,696 →
Application:
14/024,429 →
Methods and Apparatus for Decision Feedback Equalization Adaptation
Patent:
9,166,832 →
Application:
14/046,597 →
Integrated Circuits with Programmable Overdrive Capabilities
Patent:
9,444,460 →
Application:
14/087,493 →
Parallel Pseudo Random Bit Sequence Generation with Adjustable Width
Patent:
9,747,076 →
Application:
14/561,131 →
Timing Signal Adjustment for Data Storage
Patent:
9,047,934 →
Application:
14/079,306 →
Specialized Processing Block with Embedded Pipelined Accumulator Circuitry
Patent:
9,575,725 →
Application:
14/218,113 →
Invariant Code Optimization in High-Level Fpga Synthesis
Patent:
9,547,738 →
Application:
14/273,295 →
Methods for Bounding the Number of Delayed Reset Clock Cycles for Retimed Circuits
Patent:
10,354,038 →
Application:
15/352,487 →
Resistive Structure with Enhanced Thermal Dissipation
Patent:
9,768,093 →
Application:
15/061,483 →
Signal Monitoring Systems For Resolving Nyquist Zone Ambiguity
Patent:
9,680,493 →
Application:
15/271,826 →
Geometric Synthesis
Methods for Using a Multiplier Circuit to Support Multiple Sub-Multiplications Using Bit Correction and Extension
Diagnostic Testing of FPGAs for Safety Critical Systems
Digital Equalizer Adaptation Using on-Die Instrument
Tristate Multiplexers with Immunity to Aging Effects
Patent:
9,941,882 →
Application:
15/213,031 →
Partial Reconfiguration Debugging Using Hybrid Models
Patent:
10,235,485 →
Application:
15/277,376 →
Methods and Apparatus for Performing Variable and Breakout Reed Solomon Encoding
Patent:
10,218,386 →
Application:
15/359,548 →
Global Variable Optimization for Integrated Circuit Applications
Patent:
10,120,969 →
Application:
15/199,538 →
Apparatus and Methods for Calibrating Analog Circuitry in an Integrated Circuit
Configuring Programmable Integrated Circuit Device Resources as Processors
Patent:
10,452,392 →
Application:
14/600,322 →
Equalizer Circuitry Having Digitally Controlled Impedances
Patent:
9,281,974 →
Application:
13/758,739 →
Digital Signal Processing Blocks with Embedded Arithmetic Circuits
Patent:
9,207,908 →
Application:
13/752,661 →
Fast Filtering
Methods and Apparatus for Monitoring Aging Effects on an Integrated Circuit
Patent:
10,114,068 →
Application:
13/973,822 →
On-Die Capacitor (Odc) Structure
Dynamically Adjustable Decimation Filter Circuitry
Patent:
9,837,988 →
Application:
14/669,501 →
Methods and Systems for Run-Time Hardware Configuration Change Management
Patent:
9,483,282 →
Application:
14/292,060 →
Techniques For Clock Data Recovery
Patent:
9,369,266 →
Application:
14/164,851 →
Method and Apparatus for Performing and Utilizing Source Code Area Annotation
Patent:
10,303,831 →
Application:
14/960,329 →
Scalable Circuitry and Method for Control Insertion
Patent:
10,296,479 →
Application:
14/975,370 →
Circuitry and Method for Decomposable Decoder
Voltage Regulator with Jitter Control
Systems and Methods for Memory Interface Calibration
Patent:
9,323,538 →
Application:
13/539,153 →
Pipelined Direct Drive Routing Fabric
Patent:
8,963,581 →
Application:
13/630,925 →
Unique Secure Serial Id
Patent:
9,582,686 →
Application:
11/939,032 →
Hybrid Architecture for Signal Processing and Signal Processing Accelerator
Patent:
10,268,605 →
Application:
14/686,326 →
Programmable Device Configuration Methods Incorporating Retiming
Patent:
9,384,311 →
Application:
14/341,030 →
Multiple-Die Synchronous Insertion Delay Measurement Circuit and Methods
Patent:
9,595,308 →
Application:
15/086,931 →
Methods and Apparatus for Fabricating Capacitor Structures with a Terminal Shield
Patent:
9,331,026 →
Application:
14/274,499 →
Low Power Optimizations for a Floating Point Multiplier
Patent:
9,606,608 →
Application:
14/219,421 →
Methods and Systems to Automatically Connect with Interfaces
Patent:
9,304,986 →
Application:
13/920,978 →
Bipolar Junction Transistor
Patent:
9,419,076 →
Application:
14/563,363 →
Methods and Apparatus for Adjusting Transmit Signal Clipping Thresholds
Patent:
9,337,782 →
Application:
14/283,703 →
Constant False Alarm Rate Circuitry in Adaptive Target Detection of Radar Systems
Patent:
9,746,549 →
Application:
14/329,768 →
Configuring Programmable Integrated Circuit Device Resources as Processing Elements
Patent:
9,553,590 →
Application:
13/662,795 →
Polynomial Calculations Optimized for Programmable Integrated Circuit Device Structures
Patent:
9,207,909 →
Application:
13/790,106 →
Efficient Configuration of an Integrated Circuit Device Using High-Level Language
Patent:
8,806,403 →
Application:
13/923,975 →
Interposer with Programmable Power Gating Granularity
Patent:
9,059,696 →
Application:
13/957,316 →
Method and Apparatus for Performing Symbolic Timing Analysis With Spatial Variation
Patent:
10,311,196 →
Application:
15/043,432 →
Circuit Design Instrumentation for State Visualization
Patent:
9,798,842 →
Application:
14/611,031 →
Method and Apparatus for Interleaving Using Stored Initial Value
Patent:
9,065,485 →
Application:
12/985,283 →
Configurable Multi-Lane Scrambler for Flexible Protocol Support
3D Memory Based Address Generator for Computationally Efficient Architectures
Multi-Level Amplitude Signaling Receiver
Configuring Data Registers to Program a Programmable Device with a Configuration Bit Stream Without Phantom Bits
Semiconductor Device Having Mirror-Symmetric Terminals and Methods of Forming the Same
Pseudo-Random Bit Sequence Generator
Integrated Circuits with Configurable Inductors
Distributing Power with Through-Silicon-Vias
Timing Operations in an Ic with Configurable Circuits
Apparatus for Improved Communication and Associated Methods
Method and Apparatus for Processing Data and Performing Crosstalk Simulation
Patent:
10,331,827 →
Application:
13/929,536 →
Methods for Selecting Integrated Circuit Dies Based on Pre-Determined Criteria
Patent:
9,823,303 →
Application:
14/213,462 →
Method to Optimize General-Purpose Input/Output Interface Pad Assignments for Integrated Circuit
Patent:
9,842,181 →
Application:
15/162,918 →
Move Based Xor Optimization
Patent:
10,073,940 →
Application:
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System and Method for Visualization and Analysis of a Chip View Including Multiple Circuit Design Revisions
Patent:
10,331,843 →
Application:
15/277,406 →
Matrix Operations in an Integrated Circuit Device
Patent:
8,959,136 →
Application:
13/466,805 →
Apparatus and Methods for Low-Skew Channel Bonding
Patent:
8,812,893 →
Application:
13/486,482 →
Volatile Memory Elements with Soft Error Upset Immunity
Patent:
8,873,278 →
Application:
13/732,737 →
Methods for Verifying Retimed Circuits with Delayed Initialization
Method and Apparatus for Receiver Vga Adaptation
Patent:
9,166,641 →
Application:
13/928,038 →
Methods and Apparatus for Performing Digital Predistortion Using Time Domain and Frequency Domain Alignment
Patent:
9,036,734 →
Application:
13/947,620 →
Techniques For Generating Fractional Periodic Signals
Patent:
8,995,599 →
Application:
13/969,427 →
Integrated Circuits with Clock Selection Circuitry
Patent:
9,515,880 →
Application:
13/338,898 →
Qr Decomposition in an Integrated Circuit Device
Patent:
8,812,576 →
Application:
13/229,820 →
Power and Bandwidth Efficient Fft for Ddr Memory
Patent:
8,825,729 →
Application:
13/236,081 →
Adaptive Rate-Matching First-in First-Out (Fifo) System
Sector-Based Clock Routing Methods and Apparatus
Patent:
9,922,157 →
Application:
14/802,702 →
Systems and Methods for Sleep Mode Power Savings in Integrated Circuit Devices
Patent:
10,353,457 →
Application:
14/638,879 →
Integrated Circuit Package Substrates having a Common Die Dependent Region and Methods for Designing the Same
Patent:
9,780,040 →
Application:
14/454,115 →
Techniques For Generating Pulse-Width Modulation Data
Incremental Register Retiming of an Integrated Circuit Design
Techniques For Bypassing Defects In Rows Of Circuits
Patent:
9,893,732 →
Application:
15/389,292 →
Apparatus, System and Method of Location Mapping
Rotatable Architecture for Multi-Chip Package (MCP)
High-Speed, Low Power, Low Kickback Noise Comparator Suitable for a Multi-Comparator Successive Approximation Analog-to-Digital Converter (Adc)
Apparatus and Method for Security in an Integrated Circuit
Patent:
10,228,415 →
Application:
15/277,494 →
Method and Apparatus for Implementing Non-Blocking Priority Based Flow Control
Methods to Achieve Accurate Time Stamp in Ieee 1588 for System with Fec Encoder
Integrated Circuit Processing via Offload Processor
Patent:
9,166,597 →
Application:
14/242,718 →
Reconfigurable Logic Analyzer Circuitry
Patent:
9,203,408 →
Application:
14/245,291 →
Metal Routing in Advanced Process Technologies
Patent:
9,099,531 →
Application:
14/332,266 →
Specification of Latency in Programmable Device Configuration
Patent:
8,839,172 →
Application:
14/197,770 →
Configuring a Device to Debug Systems in Real-Time
Patent:
9,098,662 →
Application:
14/012,827 →
Programmable-Logic-Directed Multiplier Mapping
Systems and Methods for Dynamic Voltage and Frequency Scaling in Programmable Logic Devices
One-Step Time Stamping Of Synchronization Packets For Networked Devices
Circuitry and Methods for Implementing Galois-Field Reduction
Methods and Apparatus for Selectively Extracting and Loading Register States
Data and Clock Synchronization and Variation Compensation Apparatus and Method
Power Management for Multi-Dimensional Programmable Logic Devices
Network-On-Chip (Noc) with Flexible Data Width
Variable Impedance Communication Terminal
Circuitry and Methods for Continuous Parallel Decoder Operation
Integrated Circuit Applications Using Partial Reconfiguration
Confidential Verification of Fpga Code
Time-Division-Multiplexing of Different Protocols over a Channel of an Interface Bus Between Die
Methods for Optimizing Circuit Performance via Configurable Clock Skews
Patent:
10,037,048 →
Application:
15/464,067 →
Systolic Similarity Estimation with Two-Dimensional Sliding Window
Methods and Apparatus for Performing Timing Driven Hardware Emulation
1588 Deterministic Latency with Gearbox
Patent:
9,111,042 →
Application:
13/428,781 →
Multi-Protocol Configurable Transceiver with Independent Channel-Based Pcs in an Integrated Circuit
Patent:
8,732,375 →
Application:
12/752,641 →
Modular Direct Memory Access System
Patent:
9,053,093 →
Application:
13/974,682 →
Shared Control Logic for Multiple Queues
Patent:
8,942,248 →
Application:
12/762,987 →
Apparatus and Methods for Equalizer Adaptation
High-Speed Serial Data Signal Receiver Circuitry
Memory Blocks with Shared Address Bus Circuitry
Patent:
9,178,513 →
Application:
14/135,466 →
Methods, Systems and Apparatus for Functional Safety Implementation
Face-To-Face Through-Silicon via Multi-Chip Semiconductor Apparatus with Redistribution Layer Packaging and Methods of Assembling Same
High-Speed Core Interconnect for Multi-Die Programmable Logic Devices
First-In First-Out Buffer with Lookahead Performance Booster
Systems and Methods to Reduce Voltage Guardband
Circuits And Methods For Accessing Signals In Integrated Circuits
Three Dimensional Programmable Logic Circuit Systems And Methods
Non-Destructive Readback and Writeback for Integrated Circuit Device
Flushing Cache Lines Involving Persistent Memory
Architectural Floorplan for a Structured Asic Manufactured on a 28 Nm Cmos Process Lithographic Node or Smaller
Quick Configurable Universal Register for a Configurable Integrated Circuit Die
Electronic Chip with Under-Side Power Block
Methods and Apparatus for Adaptively Maintaining a Communications Link During Idle Mode
Patent:
9,912,369 →
Application:
14/962,390 →
Implementation of Related Clocks
Network Functions Virtualization Platforms with Function Chaining Capabilities
Orthogonal Multi-Phase Scheduling Circuitry
Modular Low Latency Electrical Sequence for Die-to-Die Interface
Methods And Apparatus For Selectively Extracting And Loading Register States
Embedded Faraday Rotators and Components for Increasing Bandwidth and/or Reducing Fiber Count in Photonics Multi Chip Packages
Power Management for Multi-Dimensional Programmable Logic Devices
System, Method and Apparatus for Race-Condition True Random Number Generator
FPGA Specialist Processing Block for Machine Learning
Apparatus and Method for Clock Phase Calibration
Stacked Programmable Integrated Circuitry with Smart Memory
Method and Apparatus for Randomizer
Methods and Apparatus for Reducing Microbumps for Inter-Die Double-Data Rate (Ddr) Transfer
Transmitter Driver Circuits And Methods
Patent:
9,948,293 →
Application:
15/346,455 →
Network Functions Virtualization Platforms with Function Chaining Capabilities
Dot Product Based Processing Elements
System and Method for Using Fabric-Graph Flow to Determine Resource Costs
Method and Apparatus for Secure Provisioning of an Integrated Circuit Device
Configuring a Programmable Device Using High-Level Language
Methods for Updating Memory Maps of a System-On-Chip
Patent:
9,852,040 →
Application:
15/065,746 →
Apparatus and Methods of Rate Control for a Sample Rate Converter
Patent:
9,112,519 →
Application:
14/136,642 →
Apparatus For Configurable Interface And Associated Methods
Patent:
9,893,727 →
Application:
15/389,210 →
Interface Bridge Between Integrated Circuit Die
Method and Apparatus for Implementing Configurable Streaming Networks
Partitioning Designs to Facilitate Certification
Prefix Network-Directed Addition
Method and Apparatus for Securing a Programmable Device Using a Kill Switch
Non-Intrusive Monitoring and Control of Integrated Circuits
Method and Apparatus for Performing Incremental Compilation Using Structural Netlist Comparison
Method and Apparatus for Performing Optimization Using Don't Care States
Patent:
8,904,318 →
Application:
14/150,424 →
Programmable Logic Device with Improved Security
Patent:
9,171,185 →
Application:
14/331,016 →
Mixed-Precision Floating-Point Arithmetic Circuitry in Specialized Processing Blocks
Systems and Methods for Detecting and Mitigating of Programmable Logic Device Tampering
Methods and Apparatus for Sequencing Multiply-Accumulate Operations
Flexible Physical Function and Virtual Function Mapping
Patent:
10,133,594 →
Application:
15/425,746 →
Scalable Network-on-Chip for High-Bandwidth Memory
Memory Controller Architecture with Improved Memory Scheduling Efficiency
Patent:
9,811,263 →
Application:
14/319,103 →
3D Field Programmable Gate Array System with Reset Management and Method of Manufacture Thereof
Patent:
9,843,328 →
Application:
15/173,507 →
Large Multiplier for Programmable Logic Device
Apparatus and Methods of Receiver Offset Calibration
Patent:
8,385,496 →
Application:
12/909,744 →
Reduced Floating-Point Precision Arithmetic Circuitry
Configuring a Programmable Logic Device Using a Configuration Bit Stream Without Phantom Bits
Distributed Double-Precision Floating-Point Addition
Method and Apparatus for Securing Programming Data of a Programmable Device
Patent:
9,305,185 →
Application:
13/740,791 →
Circuit Design Tools That Support Devices with Real-Time Phase-Locked Loop Reconfiguration Capabilities
Patent:
7,949,980 →
Application:
12/184,223 →
Circuitry for High-Bandwidth, Low-Latency Machine Learning
Integrated Circuit with Dynamically-Adjustable Buffer Space for Serial Interface
Patent:
10,339,074 →
Application:
15/496,519 →
Array Encryption Core
Patent:
9,172,537 →
Application:
14/194,206 →
Methods and Apparatus for Managing Thermal Behavior in Multichip Packages
Method and Apparatus for Performing Efficient Incremental Compilation
Patent:
8,856,713 →
Application:
13/956,120 →
Integrated Circuit (Ic) with Primary and Secondary Networks and Device Containing Such an Ic
Innovative Interconnect Design for Package Architecture to Improve Latency
Scalable 2.5D Interface Circuitry
Systems and Methods for Detecting and Mitigating Programmable Logic Device Tampering
Ic Package with Capacitors Disposed on an Interposal Layer
Systems and Methods for Multiport to Multiport Cryptography
Decision Modules
Structures for Lut-Based Arithmetic in Plds
Patent:
8,788,550 →
Application:
12/484,010 →
Multi-Channel, Multi-Lane Encryption Circuitry and Methods
Patent:
9,594,928 →
Application:
14/513,452 →
Context-Sensitive Overhead Processor
Method and Apparatus for Designing a System Using Weighted-Cost Interconnect Synthesis
Patent:
10,146,898 →
Application:
15/252,292 →
Frequency Translation Circuitry for an Interconnection in an Active Interposer of a Semiconductor Package
Method and Apparatus for Verifying Structural Correctness in Retimed Circuits
Patent:
9,824,177 →
Application:
15/079,390 →
System Level Tools to Support Fpga Partial Reconfiguration
Patent:
8,910,109 →
Application:
13/964,430 →
Programmable Logic Device with Fine-Grained Disaggregation
Scaleable Look-Up Table Based Memory
Method of Manufacturing a Power Module
Methods for Updating Memory Maps of a System-On-Chip
Method and Apparatus for Performing Register Retiming in the Presence of False Path Timing Analysis Exceptions
Stacked Programmable Integrated Circuitry with Smart Memory
Method and System for Calculating Timing Variations Considering Simultaneous Switching Noise
Patent:
9,721,047 →
Application:
14/469,337 →
Physically Unclonable Functions with Enhanced Margin Testing
Patent:
9,590,626 →
Application:
15/006,590 →
Application-Based Dynamic Heterogeneous Many-Core Systems and Methods
Hybrid Package
Thermal Management of Integrated Circuits
Integrated Circuit with Peek and Poke Protection Circuitry for a Multi-Tenant Usage Model
Multi-Segment Capacitor
Patent:
7,881,041 →
Application:
12/858,183 →
Clock Synthesis for Frequency Scaling in Programmable Logic Designs
Monitoring Electrical Substation Networks
Methods and Apparatus for Unloading Data from a Configurable Integrated Circuit
Integrated Circuits with Programmable Non-Volatile Resistive Switch Elements
Patent:
10,090,840 →
Application:
15/637,726 →
Hardware Accelerator Architecture for Processing Very-Sparse and Hyper-Sparse Matrix Data
Memory Read Circuit with N Type and P Type Pre-Charge
Method of Reporting Circuit Performance for High-Level Synthesis
High-Speed Serial Interface Circuitry for Programmable Logic Device Integrated Circuits
Patent:
7,944,235 →
Application:
12/709,360 →
Serializer Circuitry for High-Speed Serial Data Transmitters on Programmable Logic Device Integrated Circuits
Digital Adaptation Circuitry and Methods for Programmable Logic Devices
Integration of High-Speed Serial Interface Circuitry into Programmable Logic Device Architectures
Patent:
7,414,429 →
Application:
11/486,867 →
Techniques for Phase Interpolation
Patent:
7,994,837 →
Application:
12/537,634 →
Efficient Rounding Circuits and Methods in Configurable Integrated Circuit Devices
Patent:
7,948,267 →
Application:
12/702,445 →
Power Distribution Network Noise Reduction
Patent:
8,513,974 →
Application:
13/352,014 →
Methods for Memory Interface Calibration
Patent:
8,588,014 →
Application:
13/149,583 →
I/O Block for High Performance Memory Interfaces
Patent:
7,928,770 →
Application:
11/935,347 →
Configurable High Speed High Voltage Input/Output Circuit for an Ic
Patent:
8,330,488 →
Application:
13/103,024 →
Hotsocket-Compatible Body Bias Circuitry with Power-Up Current Reduction Capabilities
Patent:
7,639,041 →
Application:
12/181,313 →
Specification of Multithreading in Programmable Device Configuration
Patent:
8,645,885 →
Application:
13/733,994 →
Techniques For Adjusting Periodic Signals Based On Data Detection
Patent:
8,671,305 →
Application:
13/175,604 →
Phase-Detector-Less Method and Apparatus for Minimizing Skew Between Bonded Channel Groups
Patent:
7,908,528 →
Application:
11/747,152 →
Method and Apparatus for Performing Simultaneous Register Retiming and Combinational Resynthesis During Physical Synthesis
Patent:
8,296,696 →
Application:
12/075,488 →
Distribution and Synchronization of a Divided Clock Signal
Patent:
7,898,296 →
Application:
12/624,281 →
Real Time Feedback Compensation of Programmable Logic Memory
Patent:
7,882,408 →
Application:
11/546,743 →
Automatic Adjustment of Optimization Effort in Configuring Programmable Devices
Configuration Context Switcher with a Clocked Storage Element
Apparatus and Methods of Reducing Pre-Emphasis Voltage Jitter
Apparatus and Methods of Dynamic Transmit Equalization
Patent:
8,630,198 →
Application:
12/983,180 →
Multi-Phase-Locked Loop (Pll) Solution for Multi-Link Multi-Rate Line Card Applications
Patent:
7,512,204 →
Application:
11/084,366 →
Distributed Test System and Method
Patent:
8,005,638 →
Application:
11/877,052 →
Configurable Hybrid Adder Circuitry
Computer-Aided-Design Tools for Reducing Power Consumption in Programmable Logic Devices
Patent:
7,555,741 →
Application:
11/520,944 →
Simultaneous Switching Noise Filter Architecture and Method
Patent:
7,990,235 →
Application:
12/128,581 →
Techniques for Dynamically Adjusting the Frequency Range of Phase-Locked Loops
Patent:
7,495,517 →
Application:
11/610,892 →
Method and Apparatus for Implementing a Field Programmable Gate Array Architecture with Programmable Clock Skew
Patent:
7,818,705 →
Application:
11/102,069 →
Apparatus and Method for Generating Differential Signal Using Single-Ended Drivers
Patent:
7,411,421 →
Application:
11/296,895 →
Methods and Apparatus for Debugging a System with a Hung Data Bus
Patent:
7,412,624 →
Application:
10/940,936 →
Circuitry for Facilitating Performance of Multiply-Accumulate Operations in Programmable Logic Devices
Patent:
7,565,390 →
Application:
11/089,684 →
Integrated Hard-Wired or Partly Hard-Wired Crc Generation and/or Checking Architecture for a Physical Coding Sublayer in a Programmable Logic Device
Patent:
7,627,806 →
Application:
11/436,463 →
Heterogeneous Physical Media Attachment Circuitry for Integrated Circuit Devices
Bit Error Rate Checker Receiving Serial Data Signal from an Eye Viewer
Method and Apparatus for Improving Inductor Performance Using Multiple Strands with Transposition
Patent:
7,902,953 →
Application:
12/228,956 →
Transmitter with Multiple Phase Locked Loops
Patent:
7,821,343 →
Application:
12/229,813 →
Transceiver Link Bit Error Rate Prediction
Patent:
8,103,469 →
Application:
11/297,611 →
Dqs Resync Calibration
Patent:
7,791,375 →
Application:
12/501,398 →
Phase Interpolator Circuits and Methods
Patent:
7,915,941 →
Application:
12/496,387 →
Method and Apparatus for Serial Scan Test Data Delivery
Patent:
8,543,876 →
Application:
12/819,143 →
Method for Data Packet Classification in a Data Communications Network
Computer-Aided Design Tools and Memory Element Power Supply Circuitry for Selectively Overdriving Circuit Blocks
Patent:
8,072,237 →
Application:
12/478,713 →
Sensing Circuit
Patent:
8,441,266 →
Application:
12/537,609 →
Circuitry for Providing Programmable Decision Feedback Equalization
Patent:
7,804,892 →
Application:
11/347,527 →
Method and Apparatus for Implementing a Field Programmable Gate Array Architecture with Programmable Clock Skew
Patent:
8,640,067 →
Application:
12/807,960 →
Apparatus and Methods for Activation of an Interface on an Integrated Circuit
Patent:
8,188,774 →
Application:
12/833,718 →
Method and Apparatus for Performing Automated Timing Closure Analysis for Systems Implemented on Target Devices
Patent:
8,504,970 →
Application:
13/176,126 →
Jitter Estimation in Phase-Locked Loops
Patent:
7,890,279 →
Application:
12/189,744 →
Volatile Memory Elements with Soft Error Upset Immunity
Deskew Across High Speed Data Lanes
Patent:
8,488,729 →
Application:
12/879,706 →
Apparatus and Method for the Arithmetic Over-Ride of Look Up Table Outputs in a Programmable Logic Device
Patent:
7,812,633 →
Application:
11/584,308 →
Selectively Disabled Output
Patent:
10,720,927 →
Application:
15/400,833 →
Selectively Disabled Output
Patent:
7,479,798 →
Application:
11/435,416 →
Fractional Rate Resampling Filter on Fpga
Patent:
8,289,195 →
Application:
13/072,592 →
Novel Differential Vertical Structure for High Density, Low Layer Count Packages
Patent:
8,119,931 →
Application:
12/395,424 →
Ultrasound Signal Compression
Integrated Circuits with Asymmetric Pass Transistors
Patent:
8,921,170 →
Application:
13/408,959 →
Method and Apparatus for Providing Signal Routing Control
Patent:
8,786,308 →
Application:
13/656,479 →
Integrated Circuit Applications Using Partial Reconfiguration
Patent:
10,374,609 →
Application:
15/425,744 →
Apparatus and Methods for on-Die Temperature Sensing to Improve Fpga Performance
Circuitry for Low-Precision Deep Learning
Fpga and Os Image Build Tool
Patent:
8,863,072 →
Application:
13/922,114 →
Integrated Circuit Package with Reduced Pad Capacitance
Patent:
9,245,835 →
Application:
13/955,849 →
Configurable Multi-Standard Device Interface
Patent:
9,170,952 →
Application:
13/338,707 →
Methods and Apparatus for Reducing Electrostatic Discharge During Integrated Circuit Testing
Patent:
8,975,909 →
Application:
13/560,921 →
Method and System for Self-Contained Timing and Jitter Measurement
Patent:
8,860,433 →
Application:
13/563,529 →
Integrated Circuits with Improved Memory Interface Calibration Capabilities
Patent:
9,166,590 →
Application:
14/162,037 →
Implementation of Related Clocks
Patent:
9,000,801 →
Application:
13/802,655 →
Parallel Low and Asymmetric Rate Reed Solomon Coding
Patent:
9,032,277 →
Application:
13/469,741 →
Standalone Oam Acceleration Engine
Patent:
9,313,132 →
Application:
14/289,178 →
Methods and Apparatus for Configuring and Reconfiguring a Partial Reconfiguration Region
Patent:
9,425,802 →
Application:
14/723,876 →
Methods and Systems for Voltage Reference Power Detection
Patent:
9,086,434 →
Application:
13/312,571 →
Apparatus and Methods for Transmitter Output Swing Calibration
Patent:
8,860,469 →
Application:
13/549,228 →
Systems and Methods for Coalescing Regions on a Virtualized Programmable Logic Device
Patent:
9,698,794 →
Application:
14/978,033 →
Method and System for Reducing the Effect of Component Recovery
Patent:
9,047,215 →
Application:
13/682,727 →
Schematic Display of Connectivity in an Integrated Circuit Design
Patent:
8,924,913 →
Application:
13/922,500 →
Systems and Methods for Reducing Power Supply Noise or Jitter
Patent:
8,836,384 →
Application:
13/958,156 →
Area Efficient Series Mim Capacitor
Patent:
9,171,897 →
Application:
13/936,245 →
Circuitry and Methods for Implementing Galois-Field Reduction
A Method for Fabricating Integrated Circuits with Patterned Thermal Adjustment Layers for Design Optimization
Patent:
8,912,104 →
Application:
13/047,664 →
Method and Apparatus for Supporting Low-Latency External Memory Interfaces for Integrated Circuits
Patent:
8,930,597 →
Application:
13/151,245 →
Testing an Integrated Circuit in User Mode Using Partial Reconfiguration
Patent:
10,018,675 →
Application:
14/212,160 →
Pipelined Cascaded Digital Signal Processing Structures and Methods
Constraint Based Bit-Stream Compression in Hardware for Programmable Devices
Patent:
10,152,566 →
Application:
15/277,365 →
Matrix Decomposition Using Dataflow Techniques
Patent:
8,825,730 →
Application:
13/252,562 →
Techniques For Enabling And Disabling Transistor Legs In An Output Driver Circuit
Interface for Efficient Usage of Communication Circuitry
Patent:
10,536,174 →
Application:
15/439,017 →
Interface Bridge Between Integrated Circuit Die
Forward-Flow Selection
Patent:
9,424,043 →
Application:
13/727,837 →
Power Converter for a Memory Module
Package with Thermoelectric Power Feedback Loop
Patent:
10,600,948 →
Application:
15/362,508 →
Clock Grid For Integrated Circuit
Patent:
9,660,630 →
Application:
15/295,918 →
Pipelined Interconnect Circuitry with Double Data Rate Interconnections
High Resolution and Low Power Interpolator for Delay Chain
Patent:
10,200,046 →
Application:
15/433,853 →
Techniques for Detecting and Correcting Errors on a Ring Oscillator
Mixed Redundancy Scheme for Inter-Die Interconnects in a Multichip Package
Techniques For Testing Programmable Interconnect Resources
Patent:
10,394,981 →
Application:
15/135,113 →
Methods and Apparatus for Dynamically Configuring Soft Processors on an Integrated Circuit
Methods and Apparatus for Reducing Power in Clock Distribution Networks
Patent:
9,577,649 →
Application:
15/069,082 →
Multiplier Operable to Perform a Variety of Operations
Patent:
9,223,743 →
Application:
12/753,011 →
Methods and Apparatus for Transmitting a Signal in a Single Direction Using Bidirectional Driver Circuits
Patent:
9,520,878 →
Application:
14/529,060 →
Efficient Integrated Circuits Configuration Data Management
Register Circuitry with Asynchronous System Reset
Patent:
9,768,757 →
Application:
15/177,004 →
Methods for Specifying Processor Architectures for Programmable Integrated Circuits
Implementing Integrated Circuit Designs Using Depopulation and Repopulation Operations
Adaptive on-Chip Termination Circuitry
Patent:
9,484,916 →
Application:
14/658,656 →
Self-Stuffing Multi-Clock Fifo Requiring No Synchronizers
Hough Transformation Deinterlacing Circuitry
Patent:
9,338,392 →
Application:
14/229,480 →
Partial Reconfiguration Compatibility Detection in an Integrated Circuit Device
Patent:
9,576,095 →
Application:
14/447,279 →
Method and Apparatus for Designing and Implementing a Convolution Neural Net Accelerator
Metastability Prediction and Avoidance in Memory Arbitration Circuitry
Optimizing Ic Design Using Retiming and Presenting Design Simulation Results as Rescheduling Optimization
Lane Specific Crc
Patent:
8,775,894 →
Application:
13/168,095 →
Implementing Large Multipliers in a Programmable Integrated Circuit Device
Patent:
8,959,137 →
Application:
13/677,924 →
Systems and Methods for Supporting Both Pulse Amplitude Modulation and Quadrature Amplitude Modulation
Per Channel Thermal Management Techniques for Stacked Memory
Efficient Logic Blocks Architectures for Dense Mapping of Multipliers
Polarization Maintaining Fiber with Alignment Features
On-Die Aging Measurements for Dynamic Timing Modeling
Methods and Apparatus for Secure Implemention of Integrated Circuits
Techniques For Clock Signal Transmission In Integrated Circuits And Interposers
Integrated Circuit Device with Embedded Programmable Logic
Connectivity Between Integrated Circuit Dice in a Multi-Chip Package
Method and Apparatus for Implementing an Application Aware System on a Programmable Logic Device
Stacked Through-Silicon Vias for Multi-Device Packages
Hyperbolic Functions for Machine Learning Acceleration
Method and Apparatus for Performing Large Scale Consensus Based Clustering
Patent:
10,162,924 →
Application:
15/262,939 →
Voltage Regulator and a Method to Operate the Voltage Regulator
Patent:
9,069,369 →
Application:
13/436,660 →
Hardened Programmable Devices
Apparatus for Automatically Configured Interface and Associated Methods
Systems and Methods for Preventing Data Remanence in Memory Systems
Configurable Multi-Gate Switch Circuitry
Automated Semiconductor Design Flaw Detection System
Configurable Multi-Lane Scrambler For Flexible Protocol Support
Patent:
8,949,493 →
Application:
12/847,761 →
Method and Apparatus for Improving a Design for a System During Compilation by Performing Network Replacement
Patent:
10,162,919 →
Application:
15/159,066 →
Dual Signal Protocol Input/Output (I/O) Buffer Circuit
Patent:
10,224,911 →
Application:
15/086,887 →
An Intertwined Pair of Conductive Paths Arranged in a Dielectric Stack and Having at Least Three Metal Layers
Patent:
9,131,604 →
Application:
13/078,701 →
Method and Apparatus for Optimizing Implementation of a Soft Processor Executing a Fixed Program on a Target Device
Patent:
9,891,904 →
Application:
12/804,880 →
Resource-Saving Circuit Structures for Deeply Pipelined Systolic Finite Impulse Response Filters
Systems and Methods for Maintaining Memory Access Coherency in Embedded Memory Blocks
Distributed Multi-Die Protocol Application Interface
Systems and Methods for Extraction of Electrical Specifications from Prelayout Simulations
Patent:
10,198,545 →
Application:
15/276,412 →
Integrated Circuit with State and Data Retention
Patent:
9,383,802 →
Application:
13/922,649 →
Techniques For Handling High Voltage Circuitry In An Integrated Circuit
Patent:
9,755,647 →
Application:
15/294,588 →
Systems and Methods for Authenticating Firmware Stored on an Integrated Circuit
Techniques for Varying a Periodic Signal Based on Changes in a Data Rate
Flexible Receiver Architecture
Simd Instructions for Data Compression and Decompression
Bypassable Clocked Storage Circuitry for Dynamic Voltage-Frequency Scaling
Techniques For Alignment of Parallel Signals
Integrated Circuit Device with Embedded Programmable Logic
Latched Comparator Circuitry
Patent:
9,077,323 →
Application:
14/200,471 →
Method and Circuit for Scalable Cross Point Switching Using 3-D Die Stacking
Patent:
9,077,338 →
Application:
14/282,510 →
Systems and Methods for Digital Calibration of Successive-Approximation-Register Analog-to-Digital Converter
Patent:
9,054,721 →
Application:
14/180,115 →
Integrated Circuit System with Dynamic Decoupling and Method of Manufacture Thereof
Patent:
9,153,572 →
Application:
14/489,326 →
Efficient Controllers and Implementations for Elastic Buffers
Patent:
9,172,379 →
Application:
14/497,827 →
Digital signal processing circuitry with redundancy and bidirectional data paths
Method and Apparatus for Utilizing Estimations for Register Retiming in a Design Compilation Flow
Circuits and Methods For Data Detection
Patent:
9,136,949 →
Application:
14/175,389 →
M/A For Compiling Parallel Program Having Barrier Synchronization For Programmable Hardware
Patent:
10,599,404 →
Application:
13/486,151 →
Implementing Mixed-Precision Floating-Point Operations in a Programmable Integrated Circuit Device
Patent:
8,706,790 →
Application:
12/396,720 →
Integrated Circuit Package Routing with Reduced Crosstalk
Patent:
9,425,149 →
Application:
14/088,094 →
Methods and Apparatus for Storing Error Correction Information on a Memory Controller Circuit
Patent:
9,684,559 →
Application:
14/261,985 →
Transposition of Two-Dimensional Arrays Using Single-Buffering
Patent:
10,031,846 →
Application:
15/238,734 →
Memory with Single-Event Latchup Prevention Circuitry
Sequential Delay Analysis by Placement Engines
Patent:
8,863,067 →
Application:
12/027,260 →
System and Method for Reducing Reconfiguration Power Usage
Package Substrate Warpage Reshaping Apparatus and Method
Patent:
9,633,874 →
Application:
14/334,528 →
Method and Apparatus for Performing Timing Closure Analysis When Performing Register Retiming
Patent:
9,292,638 →
Application:
14/159,858 →
Techniques For Adjusting Latency Of A Clock Signal To Affect Supply Voltage
Patent:
10,175,734 →
Application:
15/185,484 →
Methods for Incremental Circuit Design Legalization During Physical Synthesis
Patent:
10,339,241 →
Application:
15/154,785 →
Dynamic Tag Allocation for Clock Reconvergence Pessimism Removal
Patent:
10,223,493 →
Application:
15/195,517 →
Apparatus and Associated Methods for Parallelizing Clustering and Placement
Patent:
9,594,859 →
Application:
12/040,730 →
Statically-Schedulable Feed and Drain Structure for Systolic Array Architecture
Programmable Repeater Circuits And Methods
Patent:
9,667,314 →
Application:
14/970,367 →
Methods and Apparatus for Configuring and Reconfiguring a Partial Reconfiguration Region
Configuration of a Programmable Device
Patent:
10,355,909 →
Application:
15/438,228 →
Methods and Apparatus for Automated Adaptation of Transmitter Equalizer Tap Settings
Patent:
9,876,519 →
Application:
15/582,164 →
Speculative Circuit Design Component Graphical User Interface
Patent:
10,157,250 →
Application:
15/390,076 →
Multi-Protocol Configurable Transceiver Including Configurable Deskew In An Integrated Circuit
Patent:
10,216,219 →
Application:
15/356,052 →
Calibration for Mismatch in Receiver Circuitry with Multiple Samplers
Scalable Micro Bumps Indexing and Redundancy Scheme for Homogeneous Configurable Integrated Circuit Dies
Adjusting Interrupt Priorities
Flexible Transmitter Circuitry for Integrated Circuits
Machine Learning Training Architecture for Programmable Devices
Distributed Double-Precision Floating-Point Multiplication
Register Retiming and Verification of an Integrated Circuit Design
Patent:
9,529,947 →
Application:
14/525,948 →
Preemptively Generating Statistical Feedback on a Design File and Presenting the Feedback in an Input Context
Patent:
9,417,984 →
Application:
13/749,578 →
Variable Precision Floating-Point Multiplier
Multi-Rate Transceiver Circuitry
Method and Apparatus for Performing Multiplier Regularization
Active Interposer for Localized Programmable Integrated Circuit Reconfiguration
Selectable Reconfiguration for Dynamically Reconfigurable Ip Cores
Patent:
10,127,341 →
Application:
15/494,817 →
Apparatus and Methods for Adaptive Receiver Delay Equalization
Raw Format Image Data Processing
Configurable First In First Out and Deserializer Circuitry
Block Emulation Techniques in Integrated Circuits
Patent:
8,954,907 →
Application:
13/850,244 →
Methods and Apparatus for Aligning Signals in Transceiver Circuitry
Patent:
9,106,504 →
Application:
14/055,063 →
2.5D Electronic Package
Patent:
9,583,431 →
Application:
14/538,646 →
System and Method for Receiver Equalization Adaptation
Patent:
8,958,512 →
Application:
14/057,955 →
Power Management for Pci Express
Patent:
9,467,120 →
Application:
14/135,447 →
System and Method for Creating a Scalable Monolithic Packet Processing Engine
Selectable Reconfiguration for Dynamically Reconfigurable Ip Cores
Patent:
9,633,158 →
Application:
14/538,784 →
Reversible Direction Thermal Cooling System
Implementation of Floating-Point Trigonometric Functions in an Integrated Circuit Device
Parallel Processing Error Detection and Location Circuitry for Configuration Random-Access Memory
Patent:
8,694,864 →
Application:
13/617,745 →
Method and Apparatus for Performing Fast Incremental Physical Design Optimization
Hybrid Programmable Many-Core Device with on-Chip Interconnect
Systems and Methods for Low Latency Modular Multiplication
Scaling Interface Architecture Between Memory and Programmable Logic
Chip Assemblies
Notch Filter Calibration in Lc Oscillators for Supply Noise Rejection
Modular Printed Circuit Board Separation Tool
Hardware Accelerators and Methods for Out-of-Order Processing
Floating-Point Decomposition Circuitry with Dynamic Precision
Implementing Large Multipliers in Tensor Arrays
Switch Based on Load Current
Load Balanced Decoder Systems And Methods
Rounding Circuitry for Floating-Point Mantissas
Systems And Methods For Detecting And Configuring Lanes In A Circuit System
Circuits And Methods For Detecting Decreases In A Supply Voltage In An Integrated Circuit
Transceiver Parameter Determination
Vector Processor Architectures
User Signals for Data Transmission Over a Bus Interface Protocol
Systems And Methods For Electronically Scanned Array Antennas
Non-Intrusive Monitoring and Control of Integrated Circuits
High Speed Fpga Boot-Up Through Concurrent Multi-Frame Configuration Scheme
Short Link Efficient Interconnect Circuitry
Low Latency Compact Clos Network Controller
Data Strobe Enable Circuitry
Patent:
9,001,595 →
Application:
14/147,890 →
Method and Apparatus for Implementing Layers on a Convolutional Neural Network Accelerator
Non-Intrusive Monitoring and Control of Integrated Circuits
Secure Physically Unclonable Function (Puf) Error Correction
Programmable Logic Device With Integrated Network-On-Chip
Method and Apparatus for Performing Register Retiming in the Presence of Timing Analysis Exceptions
High-Speed Core Interconnect for Multi-Die Programmable Logic Devices
Power Converter with Controller Operable in Selected Modes of Operation
Power Converter with Power Switch Operable in Controlled Current Mode
Power Gated Lookup Table Circuitry
Digital Signature Verification Engine for Reconfigurable Circuit Devices
Methods and Apparatus for Building Bus Interconnection Networks Using Programmable Interconnection Resources
Patent:
9,166,599 →
Application:
14/212,667 →
Compression Using Mu-Law Approximation
Patent:
9,467,199 →
Application:
14/669,881 →
Serial Memory Interface Circuitry for Programmable Integrated Circuits
Technologies for Providing I/O Channel Abstraction for Accelerator Device Kernels
Integrated Circuit with Dynamically-Adjustable Buffer Space for Serial Interface
Patent:
9,680,773 →
Application:
13/245,790 →
Memory Controller Architecture with Improved Memory Scheduling Efficiency
Method and Apparatus for Performing Parallel Synthesis on a Field Programmable Gate Array
Patent:
8,954,906 →
Application:
14/152,570 →
Configurable Ic Having a Routing Fabric with Storage Elements
Partial Reconfiguration and in-System Debugging
Patent:
8,686,753 →
Application:
13/441,566 →
Validating an Image for a Reconfigurable Device
Scalable 2.5D Interface Architecture
Adder Circuitry for Very Large Integers
Context-Sensitive Overhead Processor
Serial Memory Interface Circuitry for Programmable Integrated Circuits
Patent:
9,712,186 →
Application:
14/256,407 →
Method and System for Dynamic Table Line Encoding
Patent:
9,100,031 →
Application:
14/148,116 →
Scalable 2.5D Interface Circuitry
Volatile Memory Elements with Soft Error Upset Immunity
Integrating Multiple Fpga Designs by Merging Configuration Settings
Patent:
9,032,343 →
Application:
14/106,088 →
Method of Multiple Lane Distribution (Mld) Deskew
System Level Tools to Support Fpga Partial Reconfiguration
Patent:
9,141,747 →
Application:
14/538,697 →
Method and Apparatus for Relocating Design Modules While Preserving Timing Closure
Hybrid Architecture for Signal Processing and Signal Processing Accelerator
Method and Apparatus for Implementing Configurable Streaming Networks
Patent:
9,515,658 →
Application:
14/510,733 →
Coarse-Grain Programmable Routing Network for Logic Devices
Method and Apparatus for Verifying Initial State Equivalence of Changed Registers in Retimed Circuits
Patent:
10,706,203 →
Application:
15/079,518 →
Hierarchical Accelerator Registry for Optimal Performance Predictability in Network Function Virtualization
Patent:
10,409,626 →
Application:
15/287,026 →
Configuration or Data Caching for Programmable Logic Device
Multi-Rate Transceiver Circuitry
Patent:
10,129,013 →
Application:
15/415,751 →
Shielding Structure for Transmission Lines
Method and apparatus for performing parallel synthesis on a field programmable gate array
Patent:
8,661,380 →
Application:
12/070,478 →
Safety Features for High Level Design
Method & Apparatus for Performing Robust Cadence Detection in a Video Deinterlacer
Patent:
8,902,358 →
Application:
13/558,673 →
Micro-Granular Delay Testing of Configurable Ics
Apparatus for Improved Encoding and Associated Methods
Translation Circuitry for an Interconnection in an Active Interposer of a Semiconductor Package
Magnetic Device Having a Conductive Clip
Methods and Apparatus for Controlling Interface Circuitry
Micromagnetic Device and Method of Forming the Same
Interface for Parallel Configuration of Programmable Devices
Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure
Non-Intrusive Monitoring and Control of Integrated Circuits
Digital Equalizer Adaptation Using on-Die Instrument
Power Converter with Controller Operable in Selected Modes of Operation
Innovative Interconnect Design for Package Architecture to Improve Latency
Apparatus and Methods for Determining Latency of a Network Port
Decision Modules
Configuration Context Switcher with a Latch
Methods and Apparatus for Embedding an Error Correction Code in Memory Cells
System-In-Package Network Processors
Fabric Die to Fabric Die Interconnect for Modularized Integrated Circuit Devices
Methods and Apparatus for Implementing Application Specific Processors
Patent:
7,392,489 →
Application:
11/040,152 →
Heterogeneous Programmable Device and Configuration Software Adapted Therefor
Patent:
8,896,344 →
Application:
13/733,985 →
Method and Apparatus for Performing Multiple Stage Physical Synthesis
Patent:
7,996,797 →
Application:
11/704,497 →
Multi-Function, Multi-Protocol Fifo for High-Speed Communication
Patent:
9,736,086 →
Application:
13/098,361 →
Field Programmable Gate Array with Integrated Application Specific Integrated Circuit Fabric
Flexible Physical Function and Virtual Function Mapping
Apparatus for Configurable Interface and Associated Methods
Patent:
9,537,488 →
Application:
13/105,968 →
Read-Leveling Implementations for DDR3 Applications on an Fpga
Time Division Multiplexed Multiport Memory Implemented Using Single-Port Memory Elements
Integrated Circuits with Specialized Processing Blocks for Performing Floating-Point Fast Fourier Transforms and Complex Multiplication
Low Overheard High Throughput Solution for Point-to-Point Link
Methods and Apparatus for Profile-Guided Optimization of Integrated Circuits
Integrated Circuit Package with Electro-Optical Interconnect Circuitry
Communication Link Control Using Communication Interface and Programmable Logic Circuitry
Patent:
9,929,803 →
Application:
15/278,211 →
Systems and Methods for Time-Multiplexed Synchronous Logic
Patent:
9,928,332 →
Application:
14/946,227 →
Integrated Circuit Package with Inter-Die Thermal Spreader Layers
Patent:
9,966,362 →
Application:
14/605,238 →
Techniques For Adjusting Gears of an Oscillator
Patent:
8,860,482 →
Application:
13/918,739 →
Multimode Current Mirror Circuitry
Patent:
9,383,763 →
Application:
14/146,913 →
Buffered Finfet Device
Selectively Disabled Output
Patent:
8,604,823 →
Application:
12/332,789 →
Method of Forming a Magnetic Device Having a Conductive Clip
Systems and Methods for Mitigating Phase Jitter in a Periodic Signal
Patent:
7,411,464 →
Application:
11/430,469 →
Micromagnetic Device and Method of Forming the Same
Circuitry on an Integrated Circuit for Performing or Facilitating Oscilloscope, Jitter, and/or Bit-Error-Rate Tester Operations
Hybrid Multipliers Implemented Using Dsp Circuitry and Programmable Logic Circuitry
Patent:
7,269,617 →
Application:
10/712,500 →
Specifying Placement and Routing Constraints for Security and Redundancy
Patent:
8,434,044 →
Application:
12/968,128 →
Programmable Logic Device Having Logic Elements with Dedicated Hardware to Configure Look Up Tables as Registers
Patent:
7,890,910 →
Application:
11/499,451 →
Power Regulator Circuitry with Power-on-Reset Control
Patent:
7,705,659 →
Application:
11/824,838 →
Techniques Relating to Oscillators
Patent:
8,035,453 →
Application:
12/577,568 →
Power Distribution Network
Patent:
8,498,129 →
Application:
13/158,034 →
Programmable Supply Voltage Regulator for Oscillator
Patent:
7,602,260 →
Application:
11/944,386 →
Programmable Logic Device Design Tool with Simultaneous Switching Noise Awareness
Patent:
7,523,430 →
Application:
11/222,588 →
Adjustable Electrical Components Formed from Arrays of Differential Circuit Elements
Programmable Logic Device Having Complex Logic Blocks with Improved Logic Cell Functionality
Patent:
7,394,287 →
Application:
11/751,392 →
Hotsocket Detection Circuitry
Patent:
7,893,716 →
Application:
11/801,864 →
Method and Apparatus for Composing and Decomposing Low-Skew Networks
Patent:
8,046,729 →
Application:
10/998,101 →
Hardware Architecture and Scheduling for High Performance Solution to Cholesky Decomposition
Patent:
8,307,021 →
Application:
12/072,144 →
Integrated Circuits with Shared Interconnect Buses
Driver for Switch and a Method of Driving the Same
Techniques for Phase Adjustment
Patent:
8,149,038 →
Application:
12/729,114 →
Equalization Circuitry Including a Digital-to-Analog Converter Having a Voltage Divider and a Multiplexer
Patent:
8,063,807 →
Application:
12/433,310 →
Level Shifter Circuits and Methods
Patent:
7,994,821 →
Application:
12/753,389 →
Micromagnetic Device and Method of Forming the Same
Module Having a Stacked Magnetic Device and Semiconductor Device and Method of Forming the Same
Voltage-Controlled-Oscillator Circuitry with Power Supply Noise Rejection
Patent:
8,378,723 →
Application:
12/910,054 →
Look-Up Table Based Memory
Patent:
7,768,430 →
Application:
12/124,091 →
Method and Apparatus for Compiling Intellectual Property Systems Design Cores Using an Incremental Compile Design Flow
Patent:
8,370,776 →
Application:
12/157,809 →
Method and Apparatus for Performing Look Up Table Unpacking and Repacking for Resynthesis
Patent:
8,201,114 →
Application:
12/590,933 →
Method and Apparatus for Automatic Hierarchical Design Partitioning
Patent:
8,255,847 →
Application:
12/587,064 →
Securing Memory Based Ip in Fpgas
Patent:
7,952,387 →
Application:
12/234,198 →
Scan Chain Circuitry for Delay Fault Testing of Logic Circuits
Patent:
7,949,916 →
Application:
12/356,495 →
Hardened Programmable Devices
Programmable Logic Device Having Complex Logic Blocks with Improved Logic Cell Functionality
Micromagnetic Device and Method of Forming the Same
Systems and Methods for Securing a Programmable Device Against an Over-Voltage Attack
Method and Apparatus for Performing Incremental Delay Annotation
Patent:
8,015,524 →
Application:
11/803,988 →
Configurable Ic with Error Detection and Correction Circuitry
Patent:
7,669,097 →
Application:
11/391,000 →
Method and Apparatus for Performing Physical Synthesis Hill-Climbing on Multi-Processor Machines
Patent:
7,500,216 →
Application:
11/703,372 →
Implementation of Decimation Filter in Integrated Circuit Device Using Ram-Based Data Storage
Patent:
7,949,699 →
Application:
11/848,020 →
Scalable Channel Bundling with Adaptable Channel Synchronization
Patent:
8,059,677 →
Application:
12/427,960 →
Operational Cycle Assignment in a Configurable Ic
Programmable Logic Device with a Self-Power Down Mechanism
Patent:
8,106,680 →
Application:
12/172,054 →
Electronic circuit design copy protection
Patent:
8,645,712 →
Application:
11/261,155 →
Method and Apparatus for Performing Post-Placement Routability Optimization
Patent:
7,620,925 →
Application:
11/520,124 →
Method and Apparatus for Performing Integrated Global Routing and Buffer Insertion
Patent:
7,412,680 →
Application:
11/227,680 →
Configurable Input-Output (I/O) Circuitry with Pre-Emphasis Circuitry
Patent:
8,390,315 →
Application:
13/354,780 →
Prediction of Dynamic Current Waveform and Spectrum in a Semiconductor Device
Patent:
8,132,137 →
Application:
12/268,365 →
Digital Signal Processing Circuit Blocks with Support for Systolic Finite-Impulse-Response Digital Filtering
Patent:
8,458,243 →
Application:
12/716,378 →
Graphical Block-Based Design Exploration Tool
Patent:
8,407,645 →
Application:
12/354,580 →
Pld Architecture Optimized for 10G Ethernet Physical Layer Solution
Systems and Methods for Digital Calibration of Successive-Approximation-Register Analog-to-Digital Converter
Patent:
8,674,862 →
Application:
13/604,446 →
Method and Apparatus for Data Detection and Event Capture
Mixed Redundancy Scheme for Inter-Die Interconnects in a Multichip Package
Integrated Circuit Packages with Detachable Interconnect Structures
Emulation of Synchronous Pipeline Registers in Integrated Circuits with Asynchronous Interconnection Resources
Patent:
9,665,670 →
Application:
13/931,069 →
Configurable Hybrid Adder Circuitry
Patent:
9,292,474 →
Application:
13/957,113 →
Embedded Memory Blocks with Adjustable Memory Boundaries
Power Line Layout in Integrated Circuits
Patent:
9,935,052 →
Application:
14/554,667 →
Hybrid Architecture for Signal Processing and Signal Processing Accelerator
Patent:
9,647,667 →
Application:
14/686,322 →
Level-Sensitive Two-Phase Single-Wire Latch Controllers Without Contention
Patent:
9,698,784 →
Application:
15/201,048 →
Network Interface Circuitry with Flexible Memory Addressing Capabilities
Patent:
9,304,899 →
Application:
13/594,591 →
Reset Sequencing for Reducing Noise on a Power Distribution Network
Programmable Photonic-Electronic Integrated Circuit for Optical Testing
Apparatus and Associated Methods for Capacitors with Improved Density and Matching
Patent:
9,627,138 →
Application:
13/350,679 →
Addressable Test Arrays for Characterizing Integrated Circuit Device Parameters
Patent:
9,046,573 →
Application:
14/137,772 →
Methods and Apparatus for Clock Tree Phase Alignment
Patent:
8,922,264 →
Application:
13/871,812 →
Techniques for Bypassing Circuits During Tests
Patent:
9,203,412 →
Application:
14/025,199 →
Transaction Handling Between Soft Logic and Hard Logic Components of a Memory Controller
Patent:
9,424,073 →
Application:
14/297,455 →
Digital Signal Processing Circuit Blocks with Support for Systolic Finite-Impulse-Response Digital Filtering
Patent:
8,732,225 →
Application:
14/051,759 →
Techniques for Providing Clock Signals in an Integrated Circuit
Patent:
9,024,673 →
Application:
14/075,869 →
Floating-Tap Decision Feedback Equalizer
Patent:
9,025,656 →
Application:
14/106,389 →
Interconnection of an Embedded Die
Initial Condition Support for Partial Reconfiguration
Patent:
10,394,990 →
Application:
15/277,356 →
Dynamically Programmable Digital Signal Processing Blocks For Finite-Impulse-Response Filters
Patent:
9,748,928 →
Application:
15/256,223 →
Apparatus and Method of Voltage Regulation Control for Integrated Circuit
Retiming with Fixed Power-Up States
Patent:
10,296,701 →
Application:
15/195,837 →
Integrated Circuit Device with Field Programmable Optical Array
Patent:
10,212,498 →
Application:
15/470,778 →
Techniques For Fluid Cooling Of Integrated Circuits In Packages
Logic Circuits with Augmented Arithmetic Densities
Dynamic Major Mode for Efficient Memory Traffic Control
Network Processor Fpga (Npfpga): Multi-Die-Fpga Chip for Scalable Multi-Gigabit Network Processing
Integrated Circuit Device with Separate Die for Programmable Fabric and Programmable Fabric Support Circuitry
Enhancing Diagnostic Capabilities of Computing Systems by Combining Variable Patrolling Api and Comparison Mechanism of Variables
Security Policy Management for a Plurality of Dies in a System-On-Chip
Methods for Using a Multiplier to Support Multiple Sub-Multiplication Operations
Dual in-Line Memory Module (Dimm) Programmable Accelerator Card
Techniques For Signal Skew Compensation
Strong Arm Latch with Wide Common Mode Range
Accelerator Architecture on a Programmable Platform
Combined Adder and Pre-Adder for High-Radix Multiplier Circuit
Techniques for Clock Rate Changes During Data Rate Changes in an Integrated Circuit (Ic)
Techniques For Variable Forward Error Correction
Computing Floating-Point Polynomials in an Integrated Circuit Device
Patent:
9,053,045 →
Application:
13/789,882 →
A Metastability-hardened Synchronization Circuit
Patent:
9,697,309 →
Application:
12/563,095 →
Regional Design-Dependent Voltage Control and Clocking
Clock Synchronization in Multi-Die Field Programmable Gate Array Devices
Syndrome-Based Reed-Solomon Erasure Decoding Circuitry
Patent:
10,164,660 →
Application:
15/390,352 →
Bit-Alignment Testing for Obtaining Fec Code Lock
High Performance Clock Domain Crossing Fifo
Power-Aware Memory Controller Circuitry
Patent:
9,477,586 →
Application:
13/288,890 →
Method and Apparatus for Performing Clock Allocation for a System Implemented on a Programmable Device
Patent:
10,303,202 →
Application:
15/236,620 →
Method and Apparatus for Automatic Hierarchical Design Partitioning
Patent:
9,922,156 →
Application:
14/448,209 →
Apparatus and Methods for on-Die Temperature Sensing to Improve Fpga Performance
Patent:
9,735,779 →
Application:
12/534,105 →
Methods and Apparatus for Automated Integrated Circuit Package Testing
Patent:
10,048,306 →
Application:
14/635,570 →
Wafer-Level Fan-Out Wirebond Packages
Patent:
9,842,820 →
Application:
14/960,180 →
Method and Apparatus for Implementing User-Guided Speculative Register Retiming in a Compilation Flow
Patent:
10,339,244 →
Application:
14/595,375 →
Methods and Apparatus for Performing Dynamic Data Alignment for Floating-Point Operations
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9,400,635 →
Application:
13/741,266 →
Dynamically Programmable Digital Signal Processing Blocks for Finite-Impulse-Response Filters
Patent:
9,438,203 →
Application:
14/152,955 →
Esd Transistor and a Method to Design the Esd Transistor
Patent:
9,293,452 →
Application:
12/896,294 →
Techniques for Detecting and Correcting Errors on a Ring Oscillator
Methods and Apparatus for Passive Equalization in High-Speed and High Density Integrated Circuits
Patent:
9,548,278 →
Application:
14/980,894 →
Increasing Error Rate Detection through Distribution of Read Current Load
Patent:
10,446,202 →
Application:
15/338,074 →
Method and Apparatus for Relocating Design Modules While Preserving Timing Closure
Patent:
10,102,326 →
Application:
14/922,230 →
Receiver Eye-Monitor Circuit and Method
Patent:
9,319,186 →
Application:
14/245,655 →
Circuitry and Methods for Continuous Parallel Decoder Operation
Patent:
9,954,553 →
Application:
14/844,551 →
Contact Fuse
Patent:
9,153,773 →
Application:
13/214,995 →
Security Variable Scrambling
Patent:
9,425,959 →
Application:
14/025,697 →
Metal-Insulator-Metal Capacitors Between Metal Interconnect Layers
Patent:
9,331,137 →
Application:
13/431,818 →
Hierarchical Cyclic Redundancy Check Circuitry
Patent:
9,312,883 →
Application:
13/742,192 →
Adjustable Ground Shielding Circuitry
Patent:
9,583,554 →
Application:
14/581,428 →
Memory Error Detection and Correction Circuitry
Patent:
9,081,062 →
Application:
12/870,383 →
Method and System for Transitioning a Communication Circuit to a Low-Power State
Patent:
8,989,284 →
Application:
13/175,749 →
Multi-Cycle Resource Sharing
Patent:
9,430,425 →
Application:
13/727,807 →
High Performance Pcb
Patent:
8,841,561 →
Application:
12/714,156 →
Identifying the Cause of Timing Failure of an Ic Design Using Sequential Timing
Method and Apparatus for Implementing Periphery Devices on a Programmable Circuit Using Partial Reconfiguration
Apparatus and Methods of Dynamic Transmit Equalization
Patent:
9,270,500 →
Application:
14/106,485 →
Methods and Apparatus for Selectively Extracting and Loading Register States
Patent:
10,216,254 →
Application:
15/197,448 →
Method and Apparatus for Placing and Routing Partial Reconfiguration Modules
Distributed Burst Error Protection
Patent:
9,941,903 →
Application:
14/597,090 →
Apparatus and Methods for Tuning a Communication Link for Power Conservation
Patent:
9,419,746 →
Application:
14/280,351 →
Scalable Architecture for Ip Block Integration
Patent:
9,847,783 →
Application:
14/882,065 →
Processor with Cycle Offsets and Delay Lines to Allow Scheduling of Instructions Through Time
Systems and Methods for Memory Controller Reference Voltage Calibration
Patent:
9,111,603 →
Application:
13/409,077 →
Apparatus for Improving Reliability of Electronic Circuitry and Associated Methods
Decoupling Capacitor Circuitry
Transceiver system with reduced latency uncertainty
Integrated Circuit with a Self-Destruction Mechanism
Patent:
9,396,358 →
Application:
12/690,054 →
Multilayer Integrated Circuit Packages with Localized Air Structures
Patent:
9,331,370 →
Application:
13/829,883 →
Techniques to Generate a More Accurate Simulation Model
Patent:
8,893,068 →
Application:
13/461,143 →
Ternary Dsp Block
Patent:
9,164,728 →
Application:
13/471,951 →
Adjustable Drive Strength Input-Output Buffer Circuitry
Patent:
9,099,999 →
Application:
13/485,768 →
Dual-Stage Continuous-Time Linear Equalizer
Patent:
8,810,319 →
Application:
13/492,550 →
High Speed Serial Interface
Patent:
8,835,769 →
Application:
13/524,687 →
Systems and Methods for Dsp Block Enhancement
Patent:
9,069,624 →
Application:
13/555,907 →
Low-Voltage Programmable Electrical Fuses
Patent:
9,006,794 →
Application:
14/164,018 →
Priority Control Phase Shifts For Clock Signals
Patent:
9,059,720 →
Application:
14/169,680 →
Techniques for Calibrating a Clock Signal
Patent:
8,995,596 →
Application:
13/369,188 →
Programmable Matrix for the Allocation of Communication Resources
Patent:
9,077,341 →
Application:
13/802,752 →
Method and System for Operating a Communication Circuit Configurable to Support One or More Data Rates
Method and Apparatus For Implementing Periphery Devices On A Programmable Circuit Using Partial Reconfiguration
Using a Single Mask for Various Design Configurations
Patent:
9,147,611 →
Application:
14/306,956 →
Latency Built-in Self-Test
Patent:
9,100,112 →
Application:
14/331,973 →
Methods and Apparatus for Accurate Transmitter Simulation for Link Optimization
Patent:
9,178,542 →
Application:
14/548,606 →
Accelerator Architecture on a Programmable Platform
Clock and Data Recovery Circuitry with Auto-Speed Negotiation and Other Possible Features
Partial Reconfiguration Circuitry
Computationally Efficient Compression of Floating-Point Data
Data Compression for Direct Memory Access Transfers
Integrated Optical-Electronic Interface in Programmable Integrated Circuit Device
2.5D Electronic Package
Multiple Reconfiguration Profiles for Dynamically Reconfigurable Intellectual Property Cores
Patent:
9,311,106 →
Application:
14/045,643 →
Methods and Apparatus for Probing Signals from a Circuit After Register Retiming
Electronic Assembly Apparatus and Associated Methods
Conversion and Compression of Floating-Point and Integer Data
Integrated Circuit with Tamper-Detection and Self-Erase Mechanisms
Mapping Network Applications to a Hybrid Programmable Many-Core Device
Duty Cycle Distortion Correction Circuitry
Error Resilient Packaged Components
Hybrid Programmable Many-Core Device with on-Chip Interconnect
Regulator Circuitry Capable of Tracking Reference Voltages
Integrated Circuits with Error Handling Capabilities
Patent:
9,575,862 →
Application:
14/333,408 →
Techniques For Signal Skew Compensation
Patent:
10,333,535 →
Application:
15/278,409 →
Transport Network
Cache Memory Controller for Accelerated Data Transfer
Pipelined Direct Drive Routing Fabric
Patent:
9,100,011 →
Application:
14/594,832 →
NETWORK PROCESSOR FPGA (npFPGA): MULTI-DIE FPGA CHIP FOR SCALABLE MULTI-GIGABIT NETWORK PROCESSING
Patent:
9,886,072 →
Application:
13/921,364 →
Electrostatic Discharge Protection Circuits and Methods
Patent:
9,373,612 →
Application:
13/907,140 →
Systems and Methods for a Low Hold-Time Sequential Input Stage
Patent:
9,806,696 →
Application:
14/978,165 →
Cross-Point Programming of Pipelined Interconnect Circuitry
Patent:
10,289,585 →
Application:
14/464,237 →
Method and Apparatus for High-Level Programs with General Control Flow
Patent:
9,690,278 →
Application:
14/249,939 →
Distributed Burst Error Protection
Patent:
8,943,393 →
Application:
13/310,628 →
Method and System for Operating a Circuit
Patent:
8,847,624 →
Application:
13/358,449 →
Partial Reconfiguration and Error Detection in an Integrated Circuit
Patent:
8,924,818 →
Application:
13/749,396 →
Method and Apparatus For Performing Timing Analysis That Accounts For Rise/Fall Skew
Patent:
8,930,175 →
Application:
13/368,587 →
High Speed Io Buffer
Patent:
9,166,591 →
Application:
13/957,310 →
Integrated Circuits with Complementary Non-Volatile Resistive Memory Elements
Method and Apparatus for Performing Different Types of Convolution Operations with the Same Processing Elements
Configurable Storage Blocks Having Simple First-in First-Out Enabling Circuitry
Interposer with Embedded Clock Network Circuitry
Patent:
9,543,965 →
Application:
14/046,467 →
Integrated Circuit Package Substrate with Openings Surrounding a Conductive Via
Patent:
9,478,491 →
Application:
14/170,294 →
Multi-Rate Transceiver Circuitry
Interface Bridge Between Integrated Circuit Die
Method and Apparatus for Securing Programming Data of a Programmable Device
Patent:
9,870,488 →
Application:
15/090,440 →
Methods and Apparatus for Automatic Fault Detection
Programmable Logic Device Virtualization
Apparatus for Configurable Interface and Associated Methods
Method and Apparatus for Performing Incremental Compilation Using Structural Netlist Comparison
Stacked Programmable Integrated Circuitry with Smart Memory
Systems and Methods for Predictive Scheduling and Rate Limiting
Driver for Network Timing System
Patent:
10,394,734 →
Application:
15/201,006 →
Circuit Design Technique for Dqs Enable/Disable Calibration
Patent:
8,787,097 →
Application:
13/250,155 →
Circuit Structure and Method for High-Speed Forward Error Correction
Patent:
9,331,714 →
Application:
13/871,227 →
Methods and Apparatus for Programming an Integrated Circuit Using a Configuration Memory Module
Gated Clock Conversion
Patent:
8,006,206 →
Application:
12/174,632 →
High Speed Fpga Boot-Up Through Concurrent Multi-Frame Configuration Scheme
Patent:
9,401,190 →
Application:
14/685,098 →
System-In-Package Network Processors
Techniques For Transposing A Matrix Using A Memory Block
Method and Apparatus for Strobe-Based Source-Synchronous Capture Using a First-in-First-Out Unit
Patent:
8,015,382 →
Application:
11/712,143 →
FPGA Specialist Processing Block for Machine Learning
Method and Apparatus for Implementing a System-Level Design Tool for Design Planning and Architecture Exploration
Regional Partial Reconfiguration of a Programmable Device
Detailed Placement with Search and Repair
Patent:
8,984,464 →
Application:
13/681,179 →
Validating an Image for a Reconfigurable Device
Patent:
9,935,638 →
Application:
15/628,888 →
Distributed Double-Precision Floating-Point Addition
Patent:
10,061,579 →
Application:
15/367,208 →
Methods and Apparatus for Embedding an Error Correction Code in Storage Circuits
Method and Apparatus for Designing a System Using Weighted-Cost Interconnect Synthesis
Patent:
9,465,902 →
Application:
14/251,155 →
High-Level Language Code Sequence Optimization for Implementing Programmable Chip Designs
Patent:
8,578,356 →
Application:
12/966,882 →
Common Factor Mass Multiplication Circuitry
Interface for Parallel Configuration of Programmable Devices
Criticality-Based Error Detection
Overcoming Retiming Limitations Due to Initial Conditions Conflicts
Patent:
10,282,508 →
Application:
15/213,145 →
Overcoming Retiming Limitations Due to Initial Conditions Conflicts
Methods and Apparatus for Automatic Fault Detection
Programmable Logic Device Virtualization
Methods and Apparatus for High-Speed Serial Interface Link Assist
Patent:
9,465,769 →
Application:
14/982,664 →
Network-On-Chip with Fixed and Configurable Functions
Patent:
10,367,745 →
Application:
15/390,033 →
High Speed Fpga Boot-Up Through Concurrent Multi-Frame Configuration Scheme
Programmable Control Block for Dual Port Sram Application
Patent:
8,233,340 →
Application:
13/044,032 →
Clock Switch-Over Circuits and Methods
Patent:
7,911,240 →
Application:
11/750,293 →
Distributed Multi-Die Protocol Application Interface
Flexible Physical Function and Virtual Function Mapping
Compression of Processor Instructions
Patent:
7,913,065 →
Application:
11/588,100 →
Hybrid Package
Patent:
7,894,199 →
Application:
12/034,490 →
Heterogeneous High-Speed Serial Interface System with Phase-Locked Loop Architecture and Clock Distribution System
Patent:
8,700,825 →
Application:
13/679,061 →
Routing and Programming for Resistive Switch Arrays
Method and Apparatus to Build a Monolithic Mesh Interconnect with Structurally Heterogenous Tiles
Fixed-Point and Floating-Point Arithmetic Operator Circuits in Specialized Processing Blocks
Method and Apparatus for Performing Parallel Routing Using A Multi-Threaded Routing Procedure
Multi-Function, Multi-Protocol Fifo for High-Speed Communication
Method and apparatus for performing incremental compilation using structural netlist comparison
Patent:
10,275,557 →
Application:
12/655,840 →
Non-Intrusive Monitoring and Control of Integrated Circuits
Patent:
10,067,845 →
Application:
15/385,420 →
Partial Reconfiguration and in-System Debugging
Patent:
9,041,431 →
Application:
14/161,460 →
Programmable Logic Device Virtualization
Method of Accessing Stored Information in Multi-Framed Data Transmissions
Sector-Aligned Memory Accessible to Programmable Logic Fabric of Programmable Logic Device
Shielding Structure for Transmission Lines
Techniques For Protecting Security Features of Integrated Circuits
Method and Apparatus for Implementing a Processor Interface Block with an Electronic Design Automation Tool
Patent:
8,402,400 →
Application:
12/932,140 →
Multi-Layer Distributed Network
Patent:
8,166,429 →
Application:
12/253,910 →
Systems and Methods for Multiport to Multiport Cryptography
Techniques For Transposing A Matrix Using A Memory Block
Controller for a Power Converter and Method of Operating the Same
Methods and Apparatus for Managing Thermal Behavior in Multichip Packages
Common Factor Mass Multiplication Circuitry
Method of Multiple Lane Distribution (Mld) Deskew
Patent:
8,705,581 →
Application:
13/750,377 →
Systems and Methods for Routing Data Across Regions of an Integrated Circuit
Patent:
10,187,064 →
Application:
15/828,238 →
Digital Equalizer Adaptation Using on-Die Instrument
Sharing a Jtag Interface Among Multiple Partitions
Patent:
10,444,283 →
Application:
15/432,810 →
Distributed Multi-Die Protocol Application Interface
Safety Features for High Level Design
Patent:
9,690,894 →
Application:
14/930,407 →
Programmable Logic Device Virtualization
Interpolator-Based Clock and Data Recovery with Reduced Quantization Error
Patent:
9,112,646 →
Application:
14/177,987 →
Heterogeneous Hardware Accelerator Architecture for Processing Sparse Matrix Data with Skewed Non-Zero Distributions
Programmable Device Key Provisioning
Clock Synthesis for Frequency Scaling in Programmable Logic Designs
Integrated Circuit Package with Electro-Optical Interconnect Circuitry
Techniques For Heat Spreading In An Integrated Circuit
Addressable Distributed Memory in a Programmable Logic Device
Modular Periphery Tile for Integrated Circuit Device
Systems and Methods for Preventing Data Remanence in Memory Systems
Methods and Apparatus for Automatically Implementing a Compensating Reset for Retimed Circuitry
Methods and Apparatus for Accessing Configurable Memory During Hardware Emulation
Dynamic Multicycles for Core-Periphery Timing Closure
Methods and Apparatus for Reducing Reliability Degradation on an Integrated Circuit
Continuous Carry-Chain Packing
Logic Circuits with Simultaneous Dual Function Capability
Variable Delay Circuits And Methods
Reduction Operation Mapping Systems and Methods
Compute-In-Memory Systems and Methods
Methods And Apparatus For Selectively Extracting And Loading Register States
Programmable Logic Device with Fine-Grained Disaggregation
Techniques For Generating a PAM Eye Diagram in a Receiver
Integrated Circuits Having Memory with Flexible Input-Output Circuits
Embedded Network on Chip Accessible to Programmable Logic Fabric of Programmable Logic Device in Multi-Dimensional Die Systems
Efficient Dual-path Floating-Point Arithmetic Operators
Integrated Circuits with Machine Learning Extensions
Fast Memory for Programmable Devices
Network-On-Chip (Noc) with Flexible Data Width
Via Configurable Edge-Combiner with Duty Cycle Correction
Systems and Methods for Device Authentication in Supply Chain
Micro Patterns Created on the Surface to Control Placement and Uniformity of Material with Viscosity
Three Dimensional Circuit Systems And Methods Having Memory Hierarchies
Three-Dimensional Stacked Programmable Logic Fabric and Processor Design Architecture
Methods for Optimizing Circuit Performance via Configurable Clock Skews
Methods for Memory Interface Calibration
Via-Configurable High-Performance Logic Block Architecture
Technologies for Providing Inter-Kernel Flow Control for Accelerator Device Kernels
Patent:
10,789,189 →
Application:
16/395,777 →
Fast Memory for Programmable Devices
Integrated Circuits with Modular Multiplication Circuitry
Systems and Methods for Loading Weights into a Tensor Processing Block
Circuit and Method for Universal Pulse Latch
Patent:
9,941,867 →
Application:
15/270,437 →
Techniques For Reducing Uneven Aging In Integrated Circuits
Signal Detection Techniques Using Clock Data Recovery
Method and Apparatus for Performing Profile Guided Optimization for First in First Out Sizing
Side-Channel Attack Resistant Fuse Programming
Multi-Purpose Interface for Configuration Data and User Fabric Data
Apparatus and Methods for Accurate Latency Measurements in Integrated Circuits
Patent:
10,649,486 →
Application:
15/392,427 →
Stacked Semiconductor Substrates
Patent:
8,557,636 →
Application:
13/613,992 →
Clock Distribution Techniques for Channels
Patent:
7,791,370 →
Application:
12/470,455 →
Integrated Circuits with Configurable Inductors
Methods and Systems for Emulating a Synchronous Clear Port
Patent:
8,219,844 →
Application:
12/534,788 →
Voltage Controlled Oscillator Circuitry and Methods
Replacing Circuit Design Elements with Their Equivalents
Patent:
7,461,362 →
Application:
11/292,936 →
High-Speed Serial Interface Circuitry for Programmable Integrated Circuit Devices
Patent:
7,924,184 →
Application:
11/904,008 →
Common Clock Path Pessimism Analysis for Circuit Designs Using Clock Tree Networks
Robust Time Borrowing Pulse Latches
Techniques for Power Management on Integrated Circuits
Patent:
7,638,990 →
Application:
11/754,295 →
Accelerated Programming Technique for Integrated Circuits
Patent:
7,924,049 →
Application:
11/960,520 →
Wide Operating-Frequency Range Voltage Controlled Oscillators
Patent:
7,429,897 →
Application:
11/514,489 →
Multi-Protocol Multiple-Data-Rate Auto-Speed Negotiation Architecture for a Device
Systems and Methods for Providing User-Initiated Latch Up to Destroy Sram Data
Configurable Integrated Circuit with Error Correcting Circuitry
Patent:
7,529,992 →
Application:
11/390,973 →
Programmable Logic Device with Routing Channels
Patent:
7,230,451 →
Application:
11/208,906 →
Receiver Equalizer Circuitry Having Wide Data Rate and Input Common Mode Voltage Ranges
Patent:
8,222,967 →
Application:
12/644,128 →
Data Resequencing
Patent:
8,291,291 →
Application:
12/291,695 →
Logic Circuit Testing with Reduced Overhead
Patent:
7,996,743 →
Application:
12/060,805 →
Dsp Block for Implementing Large Multiplier on a Programmable Integrated Circuit Device
Patent:
8,307,023 →
Application:
12/249,051 →
Fine Tuned Pulse Width Modulation
Patent:
7,932,761 →
Application:
12/368,264 →
Techniques for Providing Clock Signals in Clock Networks
Patent:
8,581,653 →
Application:
13/328,784 →
Method and Apparatus for in-System Programmability
Patent:
7,772,881 →
Application:
11/537,519 →
Integrated Circuits with Dual-Edge Clocking
Ultrasound Signal Compression
Signal Adjustment Receiver Circuitry
Programmable Logic Device Having Logic Modules with Improved Register Capabilities
Aes Core with Independent Inputs and Outputs
Patent:
8,300,805 →
Application:
11/650,248 →
Specialized Processing Block for Programmable Integrated Circuit Device
Patent:
8,543,634 →
Application:
13/435,133 →
Method and Apparatus for Performing Hardware Assisted Placement
Patent:
8,201,126 →
Application:
12/590,643 →
Logic Structures for Ternary Addition in Logic Devices
Patent:
8,482,312 →
Application:
13/152,441 →
Systems and Methods for Generating a Test Environment and Test System Surrounding a Design of an Integrated Circuit
Patent:
8,504,973 →
Application:
13/088,300 →
Techniques for Compensating Delays in Clock Signals on Integrated Circuits
Patent:
7,619,451 →
Application:
11/670,971 →
Techniques for Selecting Phases of Clock Signals
Patent:
7,821,312 →
Application:
12/395,558 →
Integrated Circuit Guard Rings
Multi-Operand Floating Point Operations in a Programmable Integrated Circuit Device
Patent:
8,412,756 →
Application:
12/557,952 →
Methods for Instruction Trace Decomposition
Patent:
8,095,914 →
Application:
11/696,157 →
Power Reduction Techniques for Components in Integrated Circuits
Patent:
8,015,425 →
Application:
12/536,298 →
Partial Compilation of Circuit Design with New Software Version to Obtain a Complete Compiled Design
Patent:
8,245,163 →
Application:
12/178,526 →
Floating-Point Adder Circuitry with Subnormal Support
Multi-Access Memory System and a Method to Manufacture the System
Techniques for Adjusting Phases of Clock Signals
Patent:
8,860,475 →
Application:
13/853,874 →
Differential Power Analysis Resistant Encryption and Decryption Functions
Patent:
9,331,848 →
Application:
13/098,315 →
Methods and Apparatus for Testing Multiple Clock Domain Memories
Patent:
9,098,486 →
Application:
13/826,328 →
Pre-Emphasis Circuitry Including a Pre-Emphasis Voltage Variation Compensation Engine
Patent:
9,246,715 →
Application:
12/432,136 →
Compute-In-Memory Systems and Methods
Synchronize-Able Modular Physical Layer Architecture for Scalable Interface
Patent:
10,389,341 →
Application:
14/981,220 →
Circuits and Methods for Adjusting the Voltage Swing of a Signal
Patent:
9,231,631 →
Application:
14/311,192 →
On-Die Jitter Generator
Patent:
9,222,972 →
Application:
12/884,747 →
Methods for Minimizing Logic Overlap on Integrated Circuits
Patent:
10,242,144 →
Application:
15/338,134 →
Integrated Circuit Floorplans
Patent:
9,219,483 →
Application:
14/198,524 →
Methods for Fabricating Integrated Circuits with Triple Gate Oxide Devices
Patent:
9,892,922 →
Application:
13/936,066 →
Methods for Joint Optimization of Link Equalization
Patent:
9,237,044 →
Application:
13/896,518 →
Secure Partial Reconfiguration Regions
Patent:
9,577,643 →
Application:
14/090,715 →
Method and Apparatus for Phase-Aligned 2X Frequency Clock Generation
Methods and Apparatus for Rapid Interrupt Lookups
Patent:
9,811,484 →
Application:
14/319,127 →
Method and Apparatus for Improving Triggering Uniformity of Snapback Electrostatic Discharge Protection Devices
Patent:
8,946,001 →
Application:
13/349,531 →
Methods and Apparatus for Providing Redundancy on Multi-Chip Devices
Patent:
9,030,227 →
Application:
13/971,005 →
Opencl Compilation
Configurable Storage Elements
Configurable Storage Elements
Integrated Circuits with Logic Regions Having Input and Output Bypass Paths for Accessing Registers
Protocol-Agnostic Automatic Rate Negotiation for High-Speed Serial Interface in a Programmable Logic Device
Integrated Circuits with Dual-Edge Clocking
Stability-Enhanced Physically Unclonable Function Circuitry
Programmable Integrated Circuits with Redundant Circuitry
Patent:
8,860,460 →
Application:
13/669,244 →
Apparatus for Stacked Electronic Circuitry and Associated Methods
Integrated Circuit Package with Active Interposer
Parallel Decomposition of Reed Solomon Umbrella Codes
Bridge Circuitry for Communications with Dynamically Reconfigurable Circuits
Methods and Apparatus for Automated Adaptation of Transmitter Equalizer Tap Settings
Patent:
9,680,675 →
Application:
13/597,618 →
Differential Input Buffer Circuits and Methods
Patent:
9,793,893 →
Application:
15/483,796 →
Aging-Resistant Signal Path Circuitry
Patent:
10,110,229 →
Application:
15/615,704 →
Programmable Device Implementing Fixed and Floating Point Functionality in a Mixed Architecture
Patent:
10,474,429 →
Application:
15/331,024 →
Methods for Reducing Delay on Integrated Circuits by Identifying Candidate Placement Locations in a Leveled Graph
Systems And Methods For Configuring An SOPC Without A Need To Use An External Memory
Method and Apparatus for Performing Field Programmable Gate Array Packing with Continuous Carry Chains
Methods and Apparatus for Performing Fixed-Point Normalization Using Floating-Point Functional Blocks
Method and Apparatus for Implementing a Super Sample Rate Oversampling Channelizer
Methods for Handling Integrated Circuit Dies with Defects
Techniques for Variable Latency Redundancy
Patent:
10,020,812 →
Application:
15/712,953 →
Dynamic Clock-Data Phase Alignment in a Source Synchronous Interface Circuit
Interleaving Scheme for Increasing Operating Efficiency During High Current Events on an Integrated Circuit
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers
Methods and Apparatus for Performing Product Series Operations in Multiplier Accumulator Blocks
Distributed and Adaptive Heterogeneous Wireless Communication Management
Methods and Apparatus for Reducing Power Consumption in Memory Circuitry by Controlling Precharge Duration
Adjustable Empty Threshold Limit for a First-in-First-Out (Fifo) Circuit
Patent:
10,168,989 →
Application:
14/964,355 →
Distributed Double-Precision Floating-Point Addition
Patent:
10,031,752 →
Application:
15/367,205 →
Placement, Rebuffering and Routing Structure for PLD Interface
Patent:
8,901,961 →
Application:
13/687,695 →
Integrated Circuits with Machine Learning Extensions
Technologies for Efficient Reliable Compute Operations for Mission Critical Applications
Hybrid Programmable Many-Core Device with on-Chip Interconnect
Variable Precision Floating-Point Multiplier
Method and Apparatus for Host Adaptation to a Change of Persona of a Configurable Integrated Circuit Die
Built-In-Self-Test Circuits And Methods Using Pipeline Registers
Methods and Apparatus for Performing Clock and Data Duty Cycle Correction in a High-Speed Link
Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure
Distributed I/O Interfaces in Modularized Integrated Circuit Devices
Provision of on Premise Ambient Service Method and Apparatus
Techniques For Reducing Skew Between Clock Signals
Patent:
9,660,653 →
Application:
15/222,038 →
High Performance Qr Decomposition Systems and Methods
Interface Bus for Inter-Die Communication in a Multi-Chip Package Over High Density Interconnects
Method and Apparatus for Performing Non-Unique Data Pattern Detection and Alignment in a Receiver Implemented on a Field Programmable Gate Array
Techniques For Determining Timestamp Inaccuracies In A Transceiver
Protocol Analyzer for Monitoring and Debugging High-Speed Communications Links
Error Detection and Correction Circuitry
Routing-Efficient Time Division Multiplexing (Tdm) Data Path Circuitry
Patent:
10,250,347 →
Application:
15/201,052 →
Tranmission Line Bridge Interconnects
Integrated Circuit System with External Resistor to Provide Constant Current Bias and Method of Manufacture Thereof
Patent:
9,520,324 →
Application:
14/588,098 →
Methods and Apparatus for Regulating the Supply Voltage of an Integrated Circuit
Patent:
10,068,042 →
Application:
14/985,514 →
Method And Apparatus For Generating Systolic Arrays On A Target Device Using A High-Level Synthesis Language
Patent:
9,626,165 →
Application:
14/024,860 →
Multiple Plane Network-on-Chip with Master/Slave Inter-Relationships
Multichip Module with Reroutable Inter-Die Communication
Patent:
9,368,451 →
Application:
14/516,527 →
Network Functions Virtualization Platforms with Function Chaining Capabilities
Scalable Fixed-Footprint Capacitor Structure
Computing Floating-Point Polynomials in an Integrated Circuit Device
Patent:
8,949,298 →
Application:
13/234,419 →
Methods for Network Forwarding Database Flushing
Patent:
9,369,372 →
Application:
13/802,144 →
Systems And Methods For Operating A Flash Memory In An Integrated Circuit
Patent:
10,359,946 →
Application:
15/342,993 →
Method and Apparatus for Analyzing Structured Cell Candidates for Structured Application Specific Integrated Circuits
Patent:
9,251,305 →
Application:
12/287,993 →
Power Converter with Controller Operable in Selected Modes of Operation
Multi-Tier Time-Synchronization Architecture
Patent:
10,374,734 →
Application:
15/087,949 →
Behavioral Simulation Model for Clock-Data Recovery Phase-Locked Loop
Methods for Optimizing Circuit Performance via Configurable Clock Skews
Patent:
9,602,106 →
Application:
14/639,735 →
Fused Floating-Point Arithmetic Circuitry
Patent:
9,904,514 →
Application:
14/876,160 →
Packaged Integrated Circuit Including a Switch-Mode Regulator and Method of Forming the Same
Systems and Methods for Performing Profile-Based Circuit Optimization Using High-Level System Modeling
Patent:
9,529,950 →
Application:
14/661,750 →
Partial Reconfiguration of Programmable Devices
Patent:
9,590,635 →
Application:
14/958,303 →
Configurable Clock Grid Structures
Patent:
9,606,573 →
Application:
14/752,393 →
Systolic Array Based Architecture for Branch and Bound Algorithms
Patent:
9,489,338 →
Application:
14/163,570 →
Methods and Apparatus for Performing Buffer Fill Level Controlled Dynamic Power Scaling
Patent:
10,136,384 →
Application:
14/514,211 →
Digital Signal Processing Blocks with Embedded Arithmetic Circuits
Patent:
9,613,232 →
Application:
14/880,633 →
Automotive System with Motion Detection Capabilities
Interface Circuitry for Parallel Computing Architecture Circuits
Patent:
10,437,743 →
Application:
15/088,378 →
Reducing Transactional Latency in Address Decoding
Patent:
9,570,134 →
Application:
15/087,791 →
Integrated Circuits Having Expandable Processor Memory
Cmos Global Interconnect Using Multi-Voltage(or Current)-Levels
Patent:
9,559,699 →
Application:
15/004,683 →
Method and Apparatus for Performing a Single Pass Compilation for Systems with Dynamically Reconfigurable Logic Blocks
Patent:
10,102,172 →
Application:
14/979,454 →
Live Migration of Hardware Accelerated Applications
Patent:
10,169,065 →
Application:
15/197,260 →
Circuitry and Methods for Measuring and Correcting Duty-Cycle Distortion
Patent:
9,818,471 →
Application:
15/265,716 →
N-Well/P-Well Strap Structures
Apparatus for Source-Synchronous Information Transfer and Associated Methods
Integrated Circuit Retiming with Selective Modeling of Flip-Flop Secondary Signals
Patent:
10,162,918 →
Application:
15/140,327 →
Programmable Integrated Circuit with Stacked Memory Die for Storing Configuration Data
Method and Apparatus for Performing Requirement-Driven Discrete Fourier Transforms and Their Inverses
Patent:
9,229,909 →
Application:
13/667,345 →
Interface Circuitry for an Integrated Circuit System
Patent:
8,760,328 →
Application:
13/620,126 →
Apparatus and Method for Improved Integration Circuitry in Decision Feedback Equalization
Patent:
9,215,115 →
Application:
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Methods and Apparatus for Frame Detection
Patent:
9,172,505 →
Application:
13/624,095 →
Circuitry and Techniques for Calculating Scaling Factors for Crest Factor Reduction
Patent:
9,077,408 →
Application:
13/633,063 →
Integrated Circuit Package with Solderless Interconnection Structure
Patent:
9,425,174 →
Application:
14/546,296 →
Methods and Apparatus for Detecting and Correcting Errors in High-Speed Serial Communications Systems
Patent:
9,274,880 →
Application:
13/963,791 →
Techniques For Reducing Skew Between Clock Signals
Patent:
9,432,025 →
Application:
14/555,887 →
Method and Apparatus for Testing a Flip-Chip Assembly During Manufacture
Patent:
9,870,959 →
Application:
13/651,288 →
Systems And Methods For Designing An Integrated Circuit
Patent:
10,068,047 →
Application:
15/293,725 →
Differential Power Analysis Resistant Encryption and Decryption Functions
Patent:
10,320,554 →
Application:
15/139,071 →
Embedded Floating-Point Operator Circuitry
Patent:
9,552,189 →
Application:
14/497,250 →
Multi-Access Memory System and a Method to Manufacture the System
Patent:
8,749,037 →
Application:
13/284,827 →
Transceiver Circuitry with Summation Node Common Mode Droop Reduction
Patent:
9,240,912 →
Application:
14/555,035 →
Circuits and Methods For Variable Gain Amplifiers
Patent:
9,564,863 →
Application:
14/536,443 →
Methods for Built-in Self-Measurement of Jitter for Link Components
Patent:
9,596,160 →
Application:
14/529,912 →
Methods and Apparatuses for Optimizing Power and Functionality in Transistors
Patent:
10,037,992 →
Application:
14/579,831 →
Iterative Frame Synchronization for Multiple-Lane Transmission
Patent:
9,621,467 →
Application:
14/470,729 →
Integrated Circuit with a High-Speed Debug Access Port
Multi-Rate Transceiver Circuitry
Configurable Storage Elements
Generation of Distinctive Value Based on True Random Input
Integrated Circuit Resistors with Reduced Parasitic Capacitance
Patent:
8,878,334 →
Application:
13/429,284 →
Multiple-Voltage Programmable Logic Fabric
Techniques for Dividing Frequencies of Periodic Signals
Patent:
9,048,843 →
Application:
14/255,373 →
Apparatus for Field-Programmable Gate Array with Configurable Architecture and Associated Methods
Patent:
9,165,931 →
Application:
14/187,185 →
Regional Design-Dependent Voltage Control and Clocking
Patent:
10,055,526 →
Application:
15/634,902 →
Integrated Circuit Device with Embedded Programmable Logic
Adaptive Refresh Scheduling for Memory
Method and System for Operating a Communication Circuit During a Low-Power State
Patent:
9,049,120 →
Application:
13/175,740 →
Sequential Timing Using Level-Sensitive Clocked Elements to Optimize Ic Performance
Integrated Circuits with Hold Time Avoidance Circuitry
Patent:
8,866,527 →
Application:
12/753,834 →
Processor to Message-Based Network Interface Using Speculative Techniques
Techniques For Programming Circuits Using Mode Decoding
Patent:
10,128,851 →
Application:
15/823,260 →
Modular Offloading for Computationally Intensive Tasks
Patent:
9,910,705 →
Application:
14/624,951 →
Power Converter with a Dynamically Configurable Controller Based on a Power Conversion Mode
Selective Use of Different Advanced Interface Bus with Electronic Chips
Circuit Design Visibility in Integrated Circuit Devices
Analog Equalization with Peaking and Slope Control
Methods and Devices for Device Orientation to Improve Signal Quality and Sar Compliance
Analog-to-Digital Converter or Digital-to-Analog Converter Data Path with Deterministic Latency
Network-on-Chip (NOC) with Flexible Data Width
Programmable Device Implementing Fixed and Floating Point Functionality in a Mixed Architecture
Reconfigurable Digital Signal Processing (Dsp) Vector Engine
Logic Fabric Based on Microsector Infrastructure with Data Register Having Scan Registers
Scalable 2.5D Interface Circuitry
Integrated Circuit Device with Embedded Programmable Logic
Joint Channel Filtering and Crest Factor Reduction Architecture
Integrated Circuits with Machine Learning Extensions
Supply Voltage Control Systems And Methods For Integrated Circuits
Techniques For Providing Optimizations Based On Categories Of Slack In Timing Paths
Flexible Instruction Set Architecture Supporting Varying Frequencies
Systems And Methods For Logic Circuit Replacement With Configurable Circuits
Method and Apparatus for enabling Multiple Return Material Authorizations (RMAs) on an Integrated Circuit Device
Low-Latency Optical Connection for Cxl for a Server Cpu
Processor Package with Universal Optical Input/Output
Data and Clock Synchronization and Variation Compensation Apparatus and Method
Apparatus and Method to Calibrate Clock Phase Mismatches
Circuit Systems And Methods For Reducing Power Supply Voltage Droop
Voltage Regulator Circuit Systems And Methods
Methods and Apparatus for Accelerating Virtual Machine Migration
Rank-Based Dot Product Circuitry
Methods and Apparatus to Generate a Three-Dimensional (3D) Model for 3D Scene Reconstruction
Circuit Design Implementations in Secure Partitions of an Integrated Circuit
Patent:
9,946,826 →
Application:
14/843,313 →
Techniques For Reducing Uneven Aging In Integrated Circuits
Receiver Circuitry for Physical Coding Sublayer
Method and Apparatus for Supporting Automatic Testbench Parallelism and Serial Equivalence Checking During Verification
Integrated Circuits with Programmable Non-Volatile Resistive Switch Elements
Integrated Circuit Device Configuration Methods Adapted to Account for Retiming
Secure Physically Unclonable Function (Puf) Error Correction
Patent:
9,703,989 →
Application:
14/581,354 →
Circuitry for Implementing Multi-Mode Redundancy and Arithmetic Functions
Patent:
9,813,061 →
Application:
15/150,869 →
Tunable Power Distribution Network and Method of Use Thereof
Patent:
9,331,014 →
Application:
14/231,434 →
Method of Multiple Lane Distribution (Mld) Deskew
Repairable Io in an Integrated Circuit
Patent:
7,902,855 →
Application:
12/717,022 →
Routing and Programming for Resistive Switch Arrays
Patent:
9,166,598 →
Application:
13/466,847 →
Fixed-Point and Floating-Point Arithmetic Operator Circuits in Specialized Processing Blocks
Apparatus for Improved Encoding and Associated Methods
Short Link Efficient Interconnect Circuitry
Distributed Multi-Die Protocol Application Interface
Configuration Context Switcher
Enhanced Multi-Processor Waveform Data Exchange Using Compression and Decompression
Retiming Programmable Devices Incorporating Random Access Memories
Patent:
8,929,152 →
Application:
14/243,102 →
Regional Partial Reconfiguration of a Programmable Device
Methods and Devices for Reducing Clock Skew in Bidirectional Clock Trees
Patent:
9,787,311 →
Application:
15/278,295 →
Methods and Apparatus for Implementing a Saturating Multiplier
Patent:
7,487,196 →
Application:
10/918,117 →
Heterogeneous High-Speed Serial Interface System with Phase-Locked Loop Architecture and Clock Distribution System
Apparatus for Flexible Electronic Interfaces and Associated Methods
Methods and Apparatus of Time Stamping for Multi-Lane Protocols
Patent:
9,118,566 →
Application:
13/764,601 →
Time Division Multiplexed Multiport Memory Implemented Using Single-Port Memory Elements
High Performance Regularized Network-on-Chip Architecture
Fabric Die to Fabric Die Interconnect for Modularized Integrated Circuit Devices
Integrated Circuits with Interconnect Selection Circuitry
Patent:
8,854,080 →
Application:
13/941,290 →
Systems and Methods for Clock Alignment Using Pipeline Stages
Patent:
9,960,903 →
Application:
15/332,773 →
Micro-Network-On-Chip and Microsector Infrastructure
3D Field Programmable Gate Array System with Reset Management and Method of Manufacture Thereof
Patent:
9,374,094 →
Application:
14/470,901 →
Heterogeneous Programmable Device and Configuration Software Adapted Therefor
Patent:
9,030,231 →
Application:
14/455,014 →
Programmable Control Block for Dual Port Sram Application
Methods and Devices for Reducing Clock Skew in Bidirectional Clock Trees
Micro Through-Silicon via for Transistor Density Scaling
Controller for a Power Converter and Method of Operating the Same
Floating-Point Dynamic Range Expansion
Seemingly Monolithic Interface Between Separate Integrated Circuit Die
Multi-Rate Transceiver Circuitry
Dot Product Based Processing Elements
Patent:
10,339,201 →
Application:
16/102,431 →
Method and Apparatus for Performing Robust Cadence Detection in a Video Deinterlacer
Patent:
9,100,531 →
Application:
14/533,694 →
Interactive Simplification of Schematic Diagram of Integrated Circuit Design
Systems and Methods for Data Transfer Over a Shared Interface
Patent:
10,318,470 →
Application:
15/282,020 →
Method and Apparatus for Performing Fast Incremental Resynthesis
Patent:
8,484,596 →
Application:
13/614,424 →
Method and Apparatus for Performing Efficient Incremental Compilation
Patent:
8,281,274 →
Application:
12/655,864 →
Configuration Context Switcher with a Latch
Strict-Sense Minimal Spanning Switch Non-Blocking Architecture
Physically Unclonable Functions with Enhanced Margin Testing
Patent:
9,279,850 →
Application:
14/620,495 →
Data Strobe Enable Circuitry
Patent:
8,630,131 →
Application:
13/562,204 →
Compression of Floating-Point Data in Encoding Groups
Efficient Virtual I/O Address Translation
Method and Apparatus for Relocating Design Modules While Preserving Timing Closure
Power-On-Reset Circuitry
Retiming Programmable Devices Incorporating Random Access Memories
Patent:
9,251,876 →
Application:
14/560,153 →
Design Tool Selection and Implementation of Port Adapters
Patent:
8,706,931 →
Application:
12/816,316 →
Read-Leveling Implementations for DDR3 Applications on an Fpga
Error Detection and Location Circuitry for Configuration Random-Access Memory
Micro-Granular Delay Testing of Configurable Ics
System-In-Package Network Processors
Apparatus and Method for Improving Lock Time
Methods and Apparatus of Time Stamping for Multi-Lane Protocols
Patent:
9,197,531 →
Application:
13/764,614 →
Circuit Structure and Method for High-Speed Forward Error Correction
Patent:
10,374,636 →
Application:
15/090,170 →
Periphery Shoreline Augmentation for Integrated Circuits
Scaleable Look-Up Table Based Memory
Patent:
9,123,437 →
Application:
14/145,090 →
Block Floating Point Compression with Exponent Difference and Mantissa Coding
Semiconductor Device Including a Resistor Metallic Layer and Method of Forming the Same
Patent:
9,673,192 →
Application:
14/671,959 →
Clock Management Block
Patent:
8,996,906 →
Application:
12/960,459 →
Multichip Package with Protocol-Configurable Data Paths
Patent:
10,394,737 →
Application:
14/975,270 →
Apparatus for Metastability-Hardened Storage Circuits and Associated Methods
Pld Package with Coordinated Rfid Tag
Patent:
8,081,079 →
Application:
12/134,458 →
Mixed-Precision Floating-Point Arithmetic Circuitry in Specialized Processing Blocks
Method and Apparatus for Performing Fast Incremental Resynthesis
Patent:
8,732,634 →
Application:
13/908,092 →
Fixed-Point and Floating-Point Arithmetic Operator Circuits in Specialized Processing Blocks
Integrated Circuits with Specialized Processing Blocks for Performing Floating-Point Fast Fourier Transforms and Complex Multiplication
Generalized Parallel Counter Structures in Logic Devices
Patent:
8,667,045 →
Application:
13/105,133 →
Hybrid Architecture for Signal Processing
Multichip Package with Protocol-Configurable Data Paths
Multichip Package with Protocol-Configurable Data Paths
Method and Apparatus for Performing Register Retiming by Utilizing Native Timing-Driven Constraints
Patent:
10,417,374 →
Application:
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Method and Apparatus for Implementing a System-Level Design Tool for Design Planning and Architecture Exploration
Method and Apparatus for Implementing a Processor Interface Block with an Electronic Design Automation Tool
Patent:
7,895,549 →
Application:
11/986,606 →
Reconfigurable Device Bitstream Key Authentication
Integrated Circuit Device with Embedded Programmable Logic
Integrated Circuits with in-Field Diagnostic and Repair Capabilites
Feedback Control Systems with Pulse Density Signal Processing Capabilities
Techniques for Decision Feedback Equalization That Reduce Variations in the Tap Weight
Patent:
8,416,898 →
Application:
12/483,151 →
Simulation Tool for High-Speed Communications Links
Multiple Channel Bonding in a High Speed Clock Network
Patent:
8,464,088 →
Application:
12/915,794 →
Signal Detect for High-Speed Serial Interface
Patent:
7,899,649 →
Application:
12/053,884 →
Clock Duty Cycle Calibration Circuitry
Patent:
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Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jul 19, 2021
From: LANGHAMMER, MARTIN
To: INTEL CORPORATION
Reel/Frame 056899/0208 →
Assignment of Assignor's Interest
Dec 16, 2021
From: LOWE, WAYSON; WONG, BAN
To: INTEL CORPORATION
Reel/Frame 058526/0429 →
Assignment of Assignor's Interest
Apr 20, 2022
From: LIM, TEIK WAH; MONGIA, RAJIV; SRINIVASAN, ARCHANNA; IYER, MAHESH A.
To: INTEL CORPORATION
Reel/Frame 059649/0867 →
Assignment of Assignor's Interest
May 18, 2022
From: KHOR, KOK WAH
To: INTEL CORPORATION
Reel/Frame 059951/0053 →
Assignment of Assignor's Interest
Dec 7, 2022
From: LANGHAMMER, MARTIN
To: INTEL CORPORATION
Reel/Frame 062007/0877 →
Assignment of Assignor's Interest
Dec 10, 2022
From: HOSSAIN, MD ALTAF; KUMASHIKAR, MAHESH; NALAMALPU, ANKIREDDY; RAVIPALLI, SREEDHAR
To: INTEL CORPORATION
Reel/Frame 062047/0987 →
Assignment of Assignor's Interest
Jan 3, 2023
From: LANGHAMMER, MARTIN; BAECKLER, GREGG WILLIAM; GRIBOK, SERGEY VLADIMIROVICH; IYER, MAHESH A.
To: INTEL CORPORATION
Reel/Frame 062255/0200 →
Assignment of Assignor's Interest
Mar 10, 2023
From: TANG, LAI GUAN; NALAMALPU, ANKIREDDY; KUMASHIKAR, MAHESH K.; MAHESHWARI, ATUL
To: INTEL CORPORATION
Reel/Frame 062950/0802 →
Assignment of Assignor's Interest
Jun 15, 2023
From: GRIBOK, SERGEY VLADIMIROVICH; BAECKLER, GREGG WILLIAM; PASCA, BOGDAN; LANGHAMMER, MARTIN
To: INTEL CORPORATION
Reel/Frame 063966/0228 →
Assignment of Assignor's Interest
Jul 6, 2023
From: AYHAN, TOLGA; DHANOA, KULWINDER SINGH; SAFARI, NIMA; SHAHMOHAMMADIAN, MAHSHID
To: INTEL CORPORATION
Reel/Frame 064167/0674 →
Assignment of Assignor's Interest
Sep 26, 2023
From: WSZOLEK, KASPER; MAHESHWARI, ATUL; NALAMALPU, ANKIREDDY; LOH, SIANG POH
To: INTEL CORPORATION
Reel/Frame 065026/0603 →
Assignment of Assignor's Interest
Sep 27, 2023
From: NEVE DE MEVERGNIES, MICHAEL; STRONGIN, GEOFFREY
To: INTEL CORPORATION
Reel/Frame 065038/0896 →
Assignment of Assignor's Interest
Oct 5, 2023
From: LEONG, HAN HUA; TEH, TING TING
To: INTEL CORPORATION
Reel/Frame 065130/0001 →
Assignment of Assignor's Interest
Oct 10, 2023
From: CHIU, CHIA-PIN; HOSSEINI, KAVEH
To: INTEL CORPORATION
Reel/Frame 065173/0049 →
Assignment of Assignor's Interest
Oct 24, 2023
From: VENKITASUBRAMANI, ANAND; NEVE DE MEVERGNIES, MICHAEL CARL
To: INTEL CORPORATION
Reel/Frame 065325/0051 →
Assignment of Assignor's Interest
Dec 21, 2023
From: LANGHAMMER, MARTIN
To: ALTERA CORPORATION
Reel/Frame 065937/0357 →
Assignment of Assignor's Interest
Jan 19, 2024
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 066353/0886 →
Assignment of Assignor's Interest
Jan 24, 2024
From: PENG, YI; KRUEGER, NATHAN EDWARD; NAGAR, KRISHNA KUMAR; GORDON, BRANDON LEWIS
To: ALTERA CORPORATION
Reel/Frame 066228/0332 →
Assignment of Assignor's Interest
Jan 25, 2024
From: RAMADASS, KRISHNA KUMAR SIMMADHARI; DEVUNURI, VASU; BANGINWAR, RAJESH
To: INTEL CORPORATION
Reel/Frame 066249/0189 →
Assignment of Assignor's Interest
Feb 9, 2024
From: BRUNHAM, KALEN; ENGBLOM, JAKOB
To: INTEL CORPORATION
Reel/Frame 066430/0603 →
Assignment of Assignor's Interest
Mar 18, 2024
From: SRINIVASAN, ARCHANNA; LIM, TEIK WAH; CHANDRAN, PRAVIN CHANDER
To: INTEL CORPORATION
Reel/Frame 066808/0915 →
Assignment of Assignor's Interest
Feb 10, 2025
From: MEZER, AMIR; ISRAELI, TAL; PERRY, GOLAN; COHEN, MOR
To: INTEL CORPORATION
Reel/Frame 070169/0243 →
Assignment of Assignor's Interest
Feb 10, 2025
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 070159/0344 →
Assignment of Assignor's Interest
Sep 9, 2025
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 072704/0307 →
Assignment of Assignor's Interest
Dec 18, 2025
From: HERRMANN, ADAM; KELLY, ANTHONY; O'KEEFFE, CONOR; MENCHON ENRICH, RICARD
To: INTEL CORPORATION
Reel/Frame 074008/0631 →