Hybrid architecture for signal processing and signal processing accelerator
Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input ports.
1. An integrated circuit system, comprising:
programmable logic circuitry in a first region of the integrated circuit system;
an array of instruction set architecture (ISA)-based signal processors in a second region of the integrated circuit different from the first region, wherein the array of ISA-based signal processors is programmable to perform at least a filtering function; and
an interconnect network that enables communication between ISA-based signal processors of the array of ISA-based signal processors.
2. The integrated circuit system of claim 1 , wherein the programmable logic circuitry comprises field programmable gate array (FPGA) circuitry configured to send data to or receive data from the array of ISA-based signal processors.
3. The integrated circuit system of claim 1 , wherein the array of ISA-based signal processors has vector processing functionality.
4. The integrated circuit system of claim 1 , wherein the filtering function comprises digital pre-distortion (DPD) processing.
5. The integrated circuit system of claim 1 , wherein the array of ISA-based signal processors comprises distributed memory, wherein each ISA-based signal processor of the array of ISA-based signal processors is associated with at least one memory block of the distributed memory.
6. The integrated circuit system of claim 1 , wherein the interconnect network connects a first ISA-based signal processor of the array of ISA-based signal processors to a second ISA-based signal processor of the array of ISA-based signal processors to skip a third ISA-based signal processor located between the first ISA-based signal processor and the second ISA-based signal processor in the array of ISA-based signal processors.
7. The integrated circuit system of claim 6 , wherein the array of ISA-based signal processors comprises at least a first row, a second row, and a third row of ISA-based signal processors, and a first column, a second column, and a third column of ISA-based signal processors.
8. The integrated circuit system of claim 1 , comprising a hardened processing system that controls and monitors the array of ISA-based signal processors.
9. The integrated circuit system of claim 1 , wherein an ISA-based signal processor of the array of ISA-based signal processors comprises an instruction unit, a program counter, or a combination thereof.
10. The integrated circuit system of claim 9 , wherein the instruction unit stores microcode for the ISA-based signal processor.
11. The integrated circuit system of claim 9 , wherein the program counter controls a sequence of processing steps in the ISA-based signal processor.
12. An integrated circuit system, comprising:
programmable logic circuitry in a first region of the integrated circuit system;
an array of instruction set architecture (ISA)-based signal processors in a second region of the integrated circuit different from the first region; and
an interconnect network that communicatively connects a first ISA-based signal processor of the array of ISA-based signal processors to a second ISA-based signal processor of the array of ISA-based signal processors to skip a third ISA-based signal processor located between the first ISA-based signal processor and the second ISA-based signal processor in the array of ISA-based signal processors.
13. The integrated circuit system of claim 12 , wherein the array of ISA-based signal processors comprises at least a first row, a second row, and a third row of ISA-based signal processors, and a first column, a second column, and a third column of ISA-based signal processors.
14. The integrated circuit system of claim 12 , wherein the array of ISA-based signal processors is programmable to perform at least a filtering function.
15. The integrated circuit system of claim 14 , wherein the filtering function comprises digital pre-distortion (DPD) processing.
16. An integrated circuit system, comprising:
programmable logic circuitry in a first region of the integrated circuit system;
an array of instruction set architecture (ISA)-based signal processors in a second region of the integrated circuit different from the first region, wherein the array of ISA-based signal processors is programmable to perform at least a filtering function; and
a hardened processing system that controls and monitors the array of ISA-based signal processors.
17. The integrated circuit system of claim 16 , wherein the hardened processing system controls and monitors the array of ISA-based signal processors by updating contents of and configuring the array of ISA-based signal processors.
18. The integrated circuit system of claim 17 , wherein the contents comprise coefficients for the filtering function.
19. The integrated circuit system of claim 16 , wherein the filtering function comprises digital pre-distortion (DPD) processing.
20. An integrated circuit system, comprising:
field programmable gate array (FPGA) circuitry in a first region of the integrated circuit system;
an array of instruction set architecture (ISA)-based signal processors in a second region of the integrated circuit different from the first region; and
an interconnect network that communicatively connects a first ISA-based signal processor of the array of ISA-based signal processors directly to stream data to a second ISA-based signal processor of the array of ISA-based signal processors.
21. The integrated circuit system of claim 20 , wherein the interconnect network communicatively connects the first ISA-based signal processor directly to the second ISA-based signal processor using unidirectional routing circuitry.
22. The integrated circuit system of claim 20 , wherein the first ISA-based signal processor of the array of ISA-based signal processors comprises one or more output ports that stream data to the second ISA-based signal processor of the array of ISA-based signal processors.
23. The integrated circuit system of claim 21 , wherein the second ISA-based signal processor of the array of ISA-based signal processors comprises one or more input ports that receive the data from the plurality of output ports.
24. The integrated circuit system of claim 20 , wherein the array of ISA-based signal processors is programmable to perform a filtering function.
25. The integrated circuit system of claim 24 , wherein the filtering function comprises digital pre-distortion (DPD) processing.
26. A method, comprising:
receiving input data at an array of instruction set architecture (ISA)-based signal processors in a first region of an integrated circuit separate from a second region comprising programmable logic circuitry of the integrated circuit, wherein the array of ISA-based signal processors is programmable to perform at least a filtering function; and
routing communication between at least a portion of the array of ISA-based signal processors via an interconnect network.
27. The method of claim 26 , wherein the array of ISA-based signal processors has vector processing functionality.
28. The method of claim 26 , wherein routing communication between at least a portion of the array of ISA-based signal processor comprises streaming data from a first ISA-based signal processor of the array of ISA-based signal processors directly to a second ISA-based signal processor of the array of ISA-based signal processors.
29. The method of claim 26 , wherein routing communication between at least a portion of the array of ISA-based signal processor comprises connecting a first ISA-based signal processor of the array of ISA-based signal processors to a second ISA-based signal processor of the array of ISA-based signal processors to skip a third ISA-based signal processor located between the first ISA-based signal processor and the second ISA-based signal processor in the array of ISA-based signal processors.
30. The method of claim 26 , comprising transmitting instructions, via a hardened processing system, to the array of ISA-based signal processors to perform at least a filtering function.
31. The method of claim 26 , comprising, in response to routing communication between at least the portion of the array of ISA-based signal processors, implementing the portion of the array of ISA-based signal processors as a signal processor engine.
32. A method comprising:
facilitating a first portion of a filtering function using a field-programmable gate array of an integrated circuit device; and
performing a second portion of a filtering function using an array of instruction set architecture (ISA)-based signal processors of the integrated circuit device, wherein performing the second portion of the filtering function comprises:
receiving, at the array of ISA-based signal processors, at least one instruction to perform the second portion of the filtering function; and
generating output data based at least in part on the at least one instruction.
33. The method of claim 32 , wherein the filtering function comprises a digital pre-distortion (DPD) filtering function.
34. The method of claim 32 , comprising configuring one or more ISA-based signal processors of the array of ISA-based signal processors using a processing system.
35. The method of claim 32 , comprising routing interconnections between the array of instruction set architecture (ISA)-based signal processors via an interconnect network of the integrated circuit device.
36. The method of claim 32 , wherein facilitating a first portion of the filtering function comprises transmitting input signals from the field-programmable gate array to the ISA-based signal processors.