Dual in-line memory module (DIMM) programmable accelerator card
A central processing unit (CPU) may be directly coupled to an accelerator dual in-line memory module (DIMM) card that is plugged into a DIMM slot. The CPU may include a master memory controller that sends requests or offloads tasks to the accelerator DIMM card via a low-latency double data rate (DDR) interface. The acceleration DIMM card may include a slave memory controller for translating the received requests, a decoder for decoding the translated requests, control circuitry for orchestrating the data flow within the DIMM card, hardware acceleration resources that can be dynamically programmed to support a wide variety of custom functions, and input-output components for interfacing with various types of non-volatile and/or volatile memory and for connecting with other types of storage and processing devices.
1. A card, comprising:
a programmable integrated circuit having soft logic configured to operate as hardware acceleration resources, wherein the card has a dual in-line memory module (DIMM) form factor, wherein the programmable integrated circuit receives requests from a host central processing unit (CPU), wherein at least a first portion of the received requests are routed to the hardware acceleration resources for acceleration, and wherein the programmable integrated circuit is coupled to the host CPU via a transaction double data rate (DDR-T) main memory interface to facilitate implementation of the hardware acceleration resources on the programmable integrated circuit; and
memory coupled to the programmable integrated circuit, wherein a second portion of the received requests are routed to the memory without passing through the hardware acceleration resources.
2. The card of claim 1 , wherein the host CPU is coupled to another processor via a processor interface, wherein a data transfer through the DDR-T main memory interface is faster than a data transfer through the processor interface, and wherein the another processor comprises a programmable accelerator device.
3. The card of claim 2 , wherein the data transfer through the DDR-T main memory interface is at least one thousand times faster than the data transfer through the processor interface.
4. The card of claim 1 , wherein the memory comprises at least one of non-volatile memory and volatile memory.
5. The card of claim 1 , wherein the programmable integrated circuit further comprises:
a memory controller configured to translate the requests received from the host CPU; and
a request decoder configured to decode the translated requests and to route the decoded requests to a suitable destination within the card.
6. The card of claim 5 , wherein the programmable integrated circuit further comprises:
control circuitry configured to orchestrate the flow of data into and out of the programmable integrated circuit.
7. The card of claim 6 , wherein the programmable integrated circuit further comprises:
input-output components configured to interface with different types of peripheral devices formed on the card or external to the card.
8. A method of operating a computer card, comprising:
with the computer card, receiving a request from a host central processing unit (CPU), wherein the computer card has a dual in-line memory module (DIMM) form factor;
using hardware acceleration resources in the computer card to process at least some of the received requests and to generate corresponding processed data;
storing the processed data into memory in the computer card; and
with the computer card, communicating with a programmable soft logic circuit by bypassing the host CPU, wherein the programmable soft logic circuit is separate from the computer card and the host CPU.
9. The method of claim 8 , further comprising:
with a memory controller on the computer card, translating the received requests into packets; and
with a decoder on the computer card, decoding the translated requests received from the memory controller and routing the decoded requests to a suitable location in the computer card.
10. The method of claim 8 , wherein using the hardware acceleration resources in the computer card to process at least some of the received requests comprises using the hardware acceleration resources to perform a custom function selected from the group consisting of: compression/decompression, encryption/decryption, encoding/decoding, and matching.
11. The method of claim 8 , further comprising:
with the memory controller on the computer card, sending a response back to the host CPU.
12. A system, comprising:
a host processor that includes a master memory controller;
an acceleration dual in-line memory module (DIMM) card connected to the host processor via a main memory interface, wherein the acceleration DIMM card includes a slave memory controller for communicating with the master memory controller of the host processor, wherein the host processor is operable to offload a task onto the acceleration DIMM card to free up compute power on the host processor, and wherein the acceleration DIMM card includes memory for storing data associated with the offloaded task; and
a programmable coprocessor having soft logic, wherein the programmable coprocessor is separate from the acceleration DIMM card and is connected to the host processor via an additional interface having a first latency, wherein the main memory interface exhibits a second latency that is at least ten times less than the first latency, and wherein the programmable coprocessor comprises acceleration resources for the host processor.
13. The system of claim 12 , wherein the acceleration DIMM card is directly connected to the coprocessor via a bypass path.
14. The system of claim 12 , wherein the main memory interface comprises a transaction double data rate (DDR-T) interface.
15. The system of claim 14 , wherein the memory on the acceleration DIMM card comprises non-volatile memory.