Patent Assignment
Reel/Frame 066353/0886
Assignment of Assignor's Interest
Recorded: 2024-01-19
Pages: 45
Assignor
INTEL CORPORATION
Executed: 2023-12-19
Assignee
ALTERA CORPORATION
101 INNOVATION DRIVE, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(553)
Method of Manufacturing a Power Module
Encapsulated Package for a Magnetic Device
Method of Manufacturing an Encapsulated Package for a Magnetic Device
Method of Forming a Magnetic Device Having a Conductive Clip
Power Module with a Magnetic Device Having a Conductive Clip
Method of Forming a Power Module with a Magnetic Device Having a Conductive Clip
Magnetic Device Having a Conductive Clip
Controller for a Power Converter and Method of Operating the Same
Driver for Switch and a Method of Driving the Same
Dynamic Phase Alignment
Micromagnetic Device and Method of Forming the Same
Power Converter Employing a Micromagnetic Device
Method of Forming a Micromagnetic Device
Electroplating Cell and Tool
Methods of Processing a Substrate and Forming a Micromagnetic Device
Context-Sensitive Overhead Processor
Forward Error Correction Codec
Programmable Vias for Structured Asics
Power Converter with Power Switch Operable in Controlled Current Mode
Method of Accessing Stored Information in Multi-Framed Data Transmissions.
Method of Manufacturing a Power Module
Module Having a Stacked Passive Element and Method of Forming the Same
Module Having a Stacked Passive Element and Method of Forming the Same
Method of Manufacturing an Encapsulated Package for a Magnetic Device
Power Converter with a Dynamically Configurable Controller Based on a Power Conversion Mode
Power Converter with a Dynamically Configurable Controller and Output Filter
Module Having a Stacked Magnetic Device and Semiconductor Device and Method of Forming the Same
Module Having a Stacked Magnetic Device and Semiconductor Device and Method of Forming the Same
Controller for a Power Converter and Method of Operating the Same
Pseudo-random bit sequence generator
Method of Multiple Lane Distribution (Mld) Deskew
Strict-Sense Minimal Spanning Switch Non-Blocking Architecture
Mems-Based Switching
Method and Apparatus for Deskewing Data Transmissions
Method and apparatus for error-correction in and processing of GFP-T superblocks
Power Converter with Power Switch Operable in Controlled Current Mode
Power Converter with Power Switch Operable in Controlled Current Mode
Magnetic Device Having a Conductive Clip
Programming and Circuit Topologies for Programmable Vias
Application:
12/732,436 →
Publication:
US 2010/0182044
Power Converter with Controller Operable in Selected Modes of Operation
Power Converter with Controller Operable in Selected Modes of Operation
Power Converter with Controller Operable in Selected Modes of Operation
Power Converter with Controller Operable in Selected Modes of Operation
Power Converter with Controller Operable in Selected Modes of Operation
Controller for a Power Converter and Method of Operating the Same
Application:
12/971,166 →
Publication:
US 2012/0153912
Micromagnetic Device and Method of Forming the Same
Context-Sensitive Overhead Processor
Power Converter for a Memory Module
Methods of Processing a Substrate and Forming a Micromagnetic Device
Controller for a Power Converter and Method of Operating the Same
Method of Multiple Lane Distribution (Mld) Deskew
Method of Accessing Stored Information in Multi-Framed Data Transmissions
Strict-Sense Minimal Spanning Switch Non-Blocking Architecture
Architectural Floorplan for a Structured Asic Manufactured on a 28 Nm Cmos Process Lithographic Node or Smaller
Microcontroller Controlled or Direct Mode Controlled Network-Fabric on a Structured Asic
Patent:
8,677,306 →
Application:
13/649,551 →
Micromagnetic Device and Method of Forming the Same
Method of Multiple Lane Distribution (Mld) Deskew
Patent:
8,705,581 →
Application:
13/750,377 →
Context-Sensitive Overhead Processor
Strict-Sense Minimal Spanning Switch Non-Blocking Architecture
Method and Apparatus for Deskewing Data Transmissions
Eye pattern generation of unequalized eye patterns using a serial receiver with embedded eye capability
Application:
13/947,134 →
Publication:
US 2014/0133614
Semiconductor Device Including a Redistribution Layer and Metallic Pillars Coupled Thereto
Semiconductor Device Including Gate Drivers Around a Periphery Thereof
Semiconductor Device Including Alternating Source and Drain Regions, and Respective Source and Drain Metallic Strips
Apparatus Including a Semiconductor Device Coupled to a Decoupling Device
Application:
14/091,839 →
Publication:
US 2014/0159130
Micromagnetic Device and Method of Forming the Same
Method of Forming a Power Module with a Magnetic Device Having a Conductive Clip
Method of Multiple Lane Distribution (Mld) Deskew
Patent:
9,281,911 →
Application:
14/243,725 →
Pseudo-Random Bit Sequence Generator
Controller for a Power Converter and Method of Operating the Same
Power Converter for a Memory Module
Determining a Representation of an Electrical Signal
Rom Segmented Bitline Circuit
Micromagnetic Device and Method of Forming the Same
Integrated Circuit with an Increased Signal Bandwidth Input/Output (I/O) Circuit
Patent:
10,110,225 →
Application:
15/341,423 →
Methods for Delaying Register Reset for Retimed Circuits
Patent:
10,169,518 →
Application:
15/342,286 →
Transmitter Driver Circuits And Methods
Patent:
9,948,293 →
Application:
15/346,455 →
Methods for Bounding the Number of Delayed Reset Clock Cycles for Retimed Circuits
Patent:
10,354,038 →
Application:
15/352,487 →
Methods for Verifying Retimed Circuits with Delayed Initialization
Methods and Apparatus for Programmable Integrated Circuit Coprocessor Sector Management
Application:
15/358,665 →
Publication:
US 2018/0143860
Programmable Integrated Circuit with Stacked Memory Die for Storing Configuration Data
Methods and Apparatus for Performing Variable and Breakout Reed Solomon Encoding
Patent:
10,218,386 →
Application:
15/359,548 →
Package with Thermoelectric Power Feedback Loop
Patent:
10,600,948 →
Application:
15/362,508 →
Apparatus and Method of Voltage Regulation Control for Integrated Circuit
Distributed Double-Precision Floating-Point Addition
Patent:
10,031,752 →
Application:
15/367,205 →
Distributed Double-Precision Floating-Point Addition
Patent:
10,061,579 →
Application:
15/367,208 →
Automotive System with Motion Detection Capabilities
Active Interposer for Localized Programmable Integrated Circuit Reconfiguration
Memory with Single-Event Latchup Prevention Circuitry
Techniques For Bypassing Defects In Rows Of Circuits
Patent:
9,893,732 →
Application:
15/389,292 →
Methods and Apparatus for Continuous Time Linear Equalizer Tuning Using Decision Feedback Equalizer Adaptation Engine
Patent:
10,305,703 →
Application:
15/390,216 →
Methods for Determining Resistive-Capacitive Component Design Targets for Radio-Frequency Circuitry
Patent:
10,223,483 →
Application:
15/390,322 →
Syndrome-Based Reed-Solomon Erasure Decoding Circuitry
Patent:
10,164,660 →
Application:
15/390,352 →
Specialized Processing Blocks with Fixed-Point and Floating-Point Structures
Patent:
10,127,013 →
Application:
15/390,358 →
Methods for Reducing Delay on Integrated Circuits by Identifying Candidate Placement Locations in a Leveled Graph
Seemingly Monolithic Interface Between Separate Integrated Circuit Die
Interface Bridge Between Integrated Circuit Die
Apparatus and Methods for Accurate Latency Measurements in Integrated Circuits
Patent:
10,649,486 →
Application:
15/392,427 →
Techniques For Fluid Cooling Of Integrated Circuits In Packages
Configurable Storage Blocks Having Simple First-in First-Out Enabling Circuitry
Method and Apparatus for Supporting Temporal Virtualization on a Target Device
Methods and Apparatus for Performing Fixed-Point Normalization Using Floating-Point Functional Blocks
Methods and Apparatus for Automatically Implementing a Compensating Reset for Retimed Circuitry
Sharing a Jtag Interface Among Multiple Partitions
Patent:
10,101,387 →
Application:
15/429,008 →
Interface Architecture for Master-to-Master and Slave-to-Master Communication
Patent:
10,579,552 →
Application:
15/429,018 →
Programmable Photonic-Electronic Integrated Circuit for Optical Testing
Sharing a Jtag Interface Among Multiple Partitions
Patent:
10,444,283 →
Application:
15/432,810 →
Design and Manufacture of Interconnects for Integration of Multiple Integrated Circuits
Patent:
10,541,205 →
Application:
15/432,823 →
High Resolution and Low Power Interpolator for Delay Chain
Patent:
10,200,046 →
Application:
15/433,853 →
Configuration of a Programmable Device
Patent:
10,355,909 →
Application:
15/438,228 →
Prioritized Error-Detection and Scheduling
Interface for Efficient Usage of Communication Circuitry
Patent:
10,536,174 →
Application:
15/439,017 →
Embedded Multi-Die Interconnect Bridge with Improved Power Delivery
Application:
15/439,118 →
Publication:
US 2018/0240778
Pam-N Jitter/Noise Decomposition Analysis
Patent:
10,020,967 →
Application:
15/443,791 →
Criticality-Based Error Detection
Mixed-Precision Floating-Point Arithmetic Circuitry in Specialized Processing Blocks
Techniques For Heat Spreading In An Integrated Circuit
Methods and Apparatus for Accessing Configurable Memory During Hardware Emulation
Aging-Resistant Signal Path Circuitry
Patent:
10,110,229 →
Application:
15/615,704 →
Method and Apparatus for Supporting Automatic Testbench Parallelism and Serial Equivalence Checking During Verification
Methods and Apparatus for Unloading Data from a Configurable Integrated Circuit
Adjusting a Continuous Time Linear Equalization-Based Receiver
Implementation of Floating-Point Trigonometric Functions in an Integrated Circuit Device
Bit-Alignment Testing for Obtaining Fec Code Lock
Regional Design-Dependent Voltage Control and Clocking
Patent:
10,055,526 →
Application:
15/634,902 →
Methods and Apparatus for Performing Timing Driven Hardware Emulation
Methods and Apparatus for Using Load and Store Addresses to Resolve Memory Dependencies
Integrated Circuits with Programmable Non-Volatile Resistive Switch Elements
Patent:
10,090,840 →
Application:
15/637,726 →
Regional Partial Reconfiguration of a Programmable Device
Data Storage For Accelerating Functions
High Performance Qr Decomposition Systems and Methods
Floating-Point Adder Circuitry with Subnormal Support
Techniques for Variable Latency Redundancy
Patent:
10,020,812 →
Application:
15/712,953 →
Techniques For Reducing Uneven Aging In Integrated Circuits
Method of Reporting Circuit Performance for High-Level Synthesis
Systems and Methods for Region-Based Error Detection and Management in Integrated Circuits
Method and Apparatus for Reducing Constraints During Rewind Structural Verification of Retimed Circuits
Method and Apparatus for Performing Rewind Structural Verification of Retimed Circuits Driven by a Plurality of Clocks
Methods and Apparatus for Reducing Reliability Degradation on an Integrated Circuit
Systolic Similarity Estimation with Two-Dimensional Sliding Window
High Radix Subset Code Multiplier Architecture
Systems and Methods for Dynamic Voltage and Frequency Scaling in Programmable Logic Devices
Programmable Device Key Provisioning
Maintaining Reconfigurable Partitions in a Programmable Device
Dynamic Multicycles for Core-Periphery Timing Closure
Clock Synthesis for Frequency Scaling in Programmable Logic Designs
Integrated Circuit with Peek and Poke Protection Circuitry for a Multi-Tenant Usage Model
Statically-Schedulable Feed and Drain Structure for Systolic Array Architecture
Methods and Apparatus for Profile-Guided Optimization of Integrated Circuits
Integrated Circuits with Machine Learning Extensions
Techniques For Programming Circuits Using Mode Decoding
Patent:
10,128,851 →
Application:
15/823,260 →
Systems and Methods for Routing Data Across Regions of an Integrated Circuit
Patent:
10,187,064 →
Application:
15/828,238 →
Variable Delay Circuits And Methods
Distributed Programmable Delay Lines in a Clock Tree
Toggle Rate Reduction in High Level Programming Implementations
Decomposable Forward Error Correction
Reduction Operation Mapping Systems and Methods
Integrated Circuit Power Systems with Machine Learning Capabilities
Interleaving Scheme for Increasing Operating Efficiency During High Current Events on an Integrated Circuit
Scaling Interface Architecture Between Memory and Programmable Logic
Integrated Circuit Device with Separate Die for Programmable Fabric and Programmable Fabric Support Circuitry
Receiver Circuitry for Physical Coding Sublayer
Systems and Methods for Integrating Power and Thermal Management in an Integrated Circuit
Dense Digital Arithmetic Circuitry Utilization for Fixed-Point Machine Learning
Methods, Systems and Apparatus for Functional Safety Implementation
Protection Circuit for Decoupling a Low Voltage Circuitry from a High Voltage Circuitry
Interface Discovery Between Partitions of a Programmable Logic Device
Hyperbolic Functions for Machine Learning Acceleration
Sector-Aligned Memory Accessible to Programmable Logic Fabric of Programmable Logic Device
Low Latency Compact Clos Network Controller
Configuration or Data Caching for Programmable Logic Device
Methods and Apparatus for Performing Clock and Data Duty Cycle Correction in a High-Speed Link
Thermal Management of Integrated Circuits
Method and Apparatus for Performing Non-Unique Data Pattern Detection and Alignment in a Receiver Implemented on a Field Programmable Gate Array
Built-In-Self-Test Circuits And Methods Using Pipeline Registers
Programmable-Logic-Directed Multiplier Mapping
Method and Apparatus for Performing Field Programmable Gate Array Packing with Continuous Carry Chains
Dynamic Major Mode for Efficient Memory Traffic Control
Side-Channel Attack Resistant Fuse Programming
Universal Transceiver Container
Systems and Methods for Implementing Learned Parameter Systems on a Programmable Integrated Circuit
Common Factor Mass Multiplication Circuitry
Techniques For Reducing The Effects Of Aging In Logic Circuits
Methods for Handling Integrated Circuit Dies with Defects
Protocol Analyzer for Monitoring and Debugging High-Speed Communications Links
Embedded Network on Chip Accessible to Programmable Logic Fabric of Programmable Logic Device in Multi-Dimensional Die Systems
Calibration for Mismatch in Receiver Circuitry with Multiple Samplers
On-Device Bitstream Validation
Method and Apparatus for Performing Synthesis for Field Programmable Gate Array Embedded Feature Placement
Rotatable Architecture for Multi-Chip Package (MCP)
Interface Bus for Inter-Die Communication in a Multi-Chip Package Over High Density Interconnects
Innovative Interconnect Design for Package Architecture to Improve Latency
Apparatus to Synchronize Clocks of Configurable Integrated Circuit Dies Through an Interconnect Bridge
Pam-N Jitter/Noise Decomposition Analysis
Distributed Double-Precision Floating-Point Addition
Prefix Network-Directed Addition
Inter-Die Communication of Programmable Logic Devices
Method and Apparatus for Implementing a Super Sample Rate Oversampling Channelizer
Regional Design-Dependent Voltage Control and Clocking
Integrated Circuits with Programmable Non-Volatile Resistive Switch Elements
Adjusting Interrupt Priorities
Logic Circuits with Simultaneous Dual Function Capability
Integrated Circuits with Machine Learning Extensions
Methods for Using a Multiplier to Support Multiple Sub-Multiplication Operations
Floating-Point Dynamic Range Expansion
Continuous Carry-Chain Packing
Compute-In-Memory Systems and Methods
Interface for Parallel Configuration of Programmable Devices
Common Factor Mass Multiplication Circuitry
High Performance Fpga Addition
Patent:
10,340,920 →
Application:
16/147,098 →
Periphery Shoreline Augmentation for Integrated Circuits
Method and Apparatus for Performing Rewind Structural Verification of Retimed Circuits Driven by a Plurality of Clocks
Methods and Apparatus for Programming an Integrated Circuit Using a Configuration Memory Module
Time-Division-Multiplexing of Different Protocols over a Channel of an Interface Bus Between Die
Adder Circuitry for Very Large Integers
Dual in-Line Memory Module (Dimm) Programmable Accelerator Card
Method and Apparatus for Performing Multiplier Regularization
Techniques For Preventing Voltage Tampering Of Security Control Circuits
Mixed-Precision Floating-Point Arithmetic Circuitry in Specialized Processing Blocks
Methods for Using a Multiplier Circuit to Support Multiple Sub-Multiplications Using Bit Correction and Extension
On-Die Aging Measurements for Dynamic Timing Modeling
Addressable Distributed Memory in a Programmable Logic Device
Scalable Micro Bumps Indexing and Redundancy Scheme for Homogeneous Configurable Integrated Circuit Dies
Power Management for Multi-Dimensional Programmable Logic Devices
Systems and Methods for Routing Data Across Regions of an Integrated Circuit
Modular Periphery Tile for Integrated Circuit Device
Clock Synchronization in Multi-Die Field Programmable Gate Array Devices
Multi-Purpose Interface for Configuration Data and User Fabric Data
High-Speed Core Interconnect for Multi-Die Programmable Logic Devices
Flexible Transmitter Circuitry for Integrated Circuits
Regional Partial Reconfiguration of a Programmable Device
Face-To-Face Through-Silicon via Multi-Chip Semiconductor Apparatus with Redistribution Layer Packaging and Methods of Assembling Same
Method and Apparatus for Performing Profile Guided Optimization for First in First Out Sizing
Integrated Circuits Having Memory with Flexible Input-Output Circuits
Method and Apparatus for Implementing an Application Aware System on a Programmable Logic Device
Systems and Methods for Predictive Scheduling and Rate Limiting
Methods and Apparatus for Secure Implemention of Integrated Circuits
Techniques For Clock Signal Transmission In Integrated Circuits And Interposers
Network-On-Chip for Inter-Die and Intra-Die Communication in Modularized Integrated Circuit Devices
Die to Die Interconnect Structure for Modularized Integrated Circuit Devices
System-In-Package Network Processors
Circuitry for High-Bandwidth, Low-Latency Machine Learning
Active Interposer for Localized Programmable Integrated Circuit Reconfiguration
Configuration of a Programmable Device
Logic Circuits with Augmented Arithmetic Densities
Coarse-Grain Programmable Routing Network for Logic Devices
Methods and Apparatus for Providing Deterministic Latency for Communications Interfaces
Systems and Methods for Aligning Received Data
Reduced Latency Multiplier Circuitry for Very Large Numbers
Output Driver Circuit Configurable with Via Layer to Support Multiple Standards
Application:
16/456,056 →
Publication:
US 2019/0318991
Distributed I/O Interfaces in Modularized Integrated Circuit Devices
Fabric Die to Fabric Die Interconnect for Modularized Integrated Circuit Devices
High Performance Clock Domain Crossing Fifo
Geometric Synthesis
High Performance Regularized Network-on-Chip Architecture
Interface Bridge Between Integrated Circuit Die
Stacked Programmable Integrated Circuitry with Smart Memory
Integrated Circuits with Modular Multiplication Circuitry
Systems And Methods For Electronically Scanned Array Antennas
Machine Learning Training Architecture for Programmable Devices
Seemingly Monolithic Interface Between Separate Integrated Circuit Die
Security Architecture for Partial Reconfiguration of a Configurable Integrated Circuit Die
Application:
16/586,131 →
Publication:
US 2020/0167506
Via-Configurable Memory
Application:
16/586,633 →
Publication:
US 2020/0027828
Methods and Apparatus for Reducing Microbumps for Inter-Die Double-Data Rate (Ddr) Transfer
Application:
16/699,225 →
Publication:
US 2020/0097362
Methods and Apparatus for Managing Thermal Behavior in Multichip Packages
Autoencoder Neural Network for Signal Integrity Analysis of Interconnect Systems
Application:
16/720,318 →
Publication:
US 2020/0125959
Deterministic Clustering and Packing Method for Random Logic on Programmable Integrated Circuits
Techniques For Transposing A Matrix Using A Memory Block
On-Die Termination (Odt) Circuit Configurable with via Layer to Support Multiple Standards
Error Correcting Code Circuitry Compatible with Multi-Width Interfaces
Rank-Based Dot Product Circuitry
Processor Controlled Programmable Logic Device Modification
Application:
16/726,128 →
Publication:
US 2020/0133649
Translation Circuitry for an Interconnection in an Active Interposer of a Semiconductor Package
Modular Printed Circuit Board Separation Tool
Circuit and Method for Link Verification by HDCP Receiver
Quick Configurable Universal Register for a Configurable Integrated Circuit Die
Efficient Logic Blocks Architectures for Dense Mapping of Multipliers
Systems and Methods for Routing Data Across Regions of an Integrated Circuit
Coarse-Grain Programmable Routing Network for Logic Devices
Methods and Apparatus for Programming an Integrated Circuit Using a Configuration Memory Module
Orthogonal Multi-Phase Scheduling Circuitry
Floating-Point Decomposition Circuitry with Dynamic Precision
Methods and Circuitry for Boosting the Throughput of Recursive Systems
Application:
16/820,954 →
Publication:
US 2020/0218775
Modular Periphery Tile for Integrated Circuit Device
Hazard Mitigation for Lightweight Processor Cores
Interface for Parallel Configuration of Programmable Devices
High-Speed Core Interconnect for Multi-Die Programmable Logic Devices
Programmable Integrated Circuit Underlay
Constraints-Based Phased Array Calibration
Application:
16/913,868 →
Publication:
US 2020/0328789
FPGA Specialist Processing Block for Machine Learning
Implementing Large Multipliers in Tensor Arrays
Systems and Methods for Loading Weights into a Tensor Processing Block
FPGA Specialist Processing Block for Machine Learning
FPGA Specialist Processing Block for Machine Learning
Stacked Die Network Interface Controller Circuitry
Stacked Programmable Integrated Circuitry with Smart Memory
Adder Circuitry for Very Large Integers
Periphery Shoreline Augmentation for Integrated Circuits
Active Interposer for Localized Programmable Integrated Circuit Reconfiguration
Techniques For Generating a PAM Eye Diagram in a Receiver
Conductive Polygon Power and Ground Interconnects for Integrated-Circuit Packages
Application:
17/030,080 →
Publication:
US 2021/0183758
Electronic Systems For Integrated Circuits And Voltage Regulators
Characterizing Data Transmitted Over an Optical Link Based on One or More Wavelengths Used in Transmission
Application:
17/031,820 →
Publication:
US 2022/0094434
Systems and Methods for Aligning Received Data
Circuit Design Visibility in Integrated Circuit Devices
Logic Fabric Based on Microsector Infrastructure
Logic Fabric Based on Microsector Infrastructure with Data Register Having Scan Registers
Method and Apparatus for enabling Multiple Return Material Authorizations (RMAs) on an Integrated Circuit Device
Device Under Test Board with Offset Connection to Host Board
Selective Use of Different Advanced Interface Bus with Electronic Chips
Low-Latency Optical Connection for Cxl for a Server Cpu
Power Management for Multi-Dimensional Programmable Logic Devices
Systems and Methods for Predictive Scheduling and Rate Limiting
Multi-Purpose Interface for Configuration Data and User Fabric Data
Molded Fiber Connector Assembly for Pluggable Optical Mcp
Application:
17/125,497 →
Publication:
US 2022/0196939
Micro Patterns Created on the Surface to Control Placement and Uniformity of Material with Viscosity
Fiber Shuffle Embedded Optical Connector
Circuits And Methods For Programmable Memory
Application:
17/128,773 →
Publication:
US 2021/0111721
Analog-to-Digital Converter or Digital-to-Analog Converter Data Path with Deterministic Latency
Interface Bridge Between Integrated Circuit Die
Fabric Die to Fabric Die Interconnect for Modularized Integrated Circuit Devices
Micro-Network-On-Chip and Microsector Infrastructure
Non-Destructive Readback and Writeback for Integrated Circuit Device
Debug Trace Microsectors
Flushing Cache Lines Involving Persistent Memory
Systems and Methods for Low Latency Modular Multiplication
First-In First-Out Buffer with Lookahead Performance Booster
User Signals for Data Transmission Over a Bus Interface Protocol
High Performance Regularized Network-on-Chip Architecture
Integrated Circuits Having Memory with Flexible Input-Output Circuits
Techniques For Providing Optimizations Based On Categories Of Slack In Timing Paths
Integrated Circuits with Machine Learning Extensions
Vector Processor Architectures
Folded Integer Multiplication for Field-Programmable Gate Arrays
Interface Bus for Inter-Die Communication in a Multi-Chip Package Over High Density Interconnects
Application:
17/335,012 →
Publication:
US 2021/0288013
Systems And Methods For Logic Circuit Replacement With Configurable Circuits
Network-On-Chip for Inter-Die and Intra-Die Communication in Modularized Integrated Circuit Devices
Circuit Systems And Methods For Reducing Power Supply Voltage Droop
Supply Voltage Control Systems And Methods For Integrated Circuits
Voltage Regulator Circuit Systems And Methods
Circuits And Methods For Detecting Decreases In A Supply Voltage In An Integrated Circuit
Three Dimensional Programmable Logic Circuit Systems And Methods
Joint Channel Filtering and Crest Factor Reduction Architecture
Systems And Methods For Detecting And Configuring Lanes In A Circuit System
Soft Network-on-Chip Overlay Through a Partial Reconfiguration Region
FPGA Processing Block for Machine Learning or Digital Signal Processing Operations
Application:
17/358,923 →
Publication:
US 2021/0326111
Systems and Methods for Supporting Both Pulse Amplitude Modulation and Quadrature Amplitude Modulation
At-Speed Burst Sampling for User Registers
High Precision Decomposable Dsp Entity
Field-Configurable Optical Switch Implementations Within Multi-Chip Packages
Application:
17/359,374 →
Publication:
US 2022/0413216
Seemingly Monolithic Interface Between Separate Integrated Circuit Die
Modular Periphery Tile for Integrated Circuit Device
Methods and Apparatus for Reducing Reliability Degradation on an Integrated Circuit
Application:
17/406,534 →
Publication:
US 2021/0383049
High-Speed Core Interconnect for Multi-Die Programmable Logic Devices
Face-To-Face Through-Silicon via Multi-Chip Semiconductor Apparatus with Redistribution Layer Packaging and Methods of Assembling Same
Innovative Interconnect Design for Package Architecture to Improve Latency
Programmable Memory Controller Circuits And Methods
Systems And Methods For Transmitting And Receiving Auxiliary Data
Systems And Methods For Circuit Design Dependent Programmable Maximum Junction Temperatures
Interrupt Handling by Migrating Interrupts Between Processing Cores
Device, Method and System to Determine Calibration Information with a Shared Ring Oscillator Circuit
Configurable Clock Macro Circuits And Methods
Circuits And Methods For Routing Crossbars With Programmable Vias
Techniques for Monitoring and Control of High Speed Serial Communication Link
Thermal Management of Integrated Circuits
Fast Fourier Transform (FFT) Based Digital Signal Processing (DSP) Engine
Via Configurable Edge-Combiner with Duty Cycle Correction
Integrated Circuits with Machine Learning Extensions
Clock Synthesis for Frequency Scaling in Programmable Logic Designs
Methods and Apparatus for Managing Thermal Behavior in Multichip Packages
Low Latency Compact Clos Network Controller
Systems and Methods for Sparsity Operations in a Specialized Processing Block
Application:
17/485,123 →
Publication:
US 2022/0012012
Methods and Apparatus to Expose a Microservice to a Software Layer
Techniques For Reducing Uneven Aging In Integrated Circuits
Circuits And Methods For Accessing Signals In Integrated Circuits
System-In-Package Network Processors
Network Systems And Methods For Word Based Arbitration Of Data
Frequency Translation Circuitry for an Interconnection in an Active Interposer of a Semiconductor Package
Distributed Attestation in Heterogenous Computing Clusters
Machine Learning Training Architecture for Programmable Devices
Application:
17/552,436 →
Publication:
US 2022/0107783
Polarization Maintaining Fiber with Alignment Features
Memory Circuits And Methods With Write Assist
Application:
17/553,439 →
Publication:
US 2022/0108733
Systems And Methods For Configurable Interface Circuits
Systems And Methods For Generating Placements For Circuit Designs Using Pyramidal Flows
Methods and Apparatus to Derive and Verify Virtual Physical Unclonable Keys
Application:
17/556,979 →
Publication:
US 2022/0116234
Systems and Methods for Structured Mixed-Precision in a Specialized Processing Block
Systems and Methods to Reduce Voltage Guardband
Controlled Transition Between Configuration Mode and User Mode to Reduce Current-Resistance Voltage Drop
Dynamic Provisioning of Pcie Devices at Run Time for Bare Metal Servers
Application:
17/559,427 →
Publication:
US 2022/0156211
Power Allocation using Multiple Voltage Domains for Programmable Logic Devices
Application:
17/559,569 →
Publication:
US 2022/0116045
Dynamic Loadlines for Programmable Fabric Devices
Workload-Dependent Integrated Circuit Operation Based on Power Headroom
Reticle Stitching to Achieve High-Capacity Integrated Circuit
Embedded Arithmetic Blocks for Structured ASICs
Application:
17/559,851 →
Publication:
US 2023/0195416
Systems and Methods for Communicating Encrypted Time-Related Data
Circuits And Methods For Sub-Bank Sharing Of External Interfaces
Application:
17/560,086 →
Publication:
US 2022/0115047
Systems and Methods for Calculating Large Polynomial Multiplications
Application:
17/560,838 →
Publication:
US 2022/0188072
Circuitry for High-Bandwidth, Low-Latency Machine Learning
Systems and Methods for Low Power Modes for Programmable Logic Devices
Systems And Methods For Processor Circuits
Interface Bridge Between Integrated Circuit Die
Embedded Multi-Die Interconnect Bridge with Improved Power Delivery
Application:
17/581,751 →
Publication:
US 2022/0149029
Processing Module, Integrated Development Environment, Methods, and Program Codes
Application:
17/643,852 →
Publication:
US 2022/0171659
Processing Unit, Software module, Methods and Program Codes
Application:
17/643,854 →
Publication:
US 2022/0129252
Hyperbolic Functions for Machine Learning Acceleration
Application:
17/677,556 →
Publication:
US 2022/0230057
Load Balanced Decoder Systems And Methods
Circuits And Methods For Configurable Scan Chains
Temperature Control Systems And Methods For Integrated Circuits
Application:
17/703,181 →
Publication:
US 2022/0215147
Freeze And Clear Logic Circuits And Methods For Integrated Circuits
Embedded Network on Chip Accessible to Programmable Logic Fabric of Programmable Logic Device in Multi-Dimensional Die Systems
Security on Die-to-Die Interconnect
Application:
17/711,779 →
Publication:
US 2022/0229941
Clocking Architecture for a Multi-Die Package
Application:
17/711,784 →
Publication:
US 2022/0224342
Systems and Methods for Dynamic Power and Thermal Management for Programmable Logic Devices
Fabric Memory Network-On-Chip
Application:
17/711,840 →
Publication:
US 2022/0221986
Floating-Point Dynamic Range Expansion
Stacked Programmable Integrated Circuitry with Smart Memory
Embedded Multi-Die Interconnect Bridge with Improved Power Delivery
Application:
17/716,928 →
Publication:
US 2022/0230993
Fabric Memory Network-On-Chip Extension to ALM Registers and LUTRAM
Application:
17/725,307 →
Publication:
US 2022/0244867
Techniques For Reduction Of Degradation In Channels Caused By Bias Temperature Instability
Application:
17/740,704 →
Publication:
US 2022/0268837
Systems And Methods For Tracking Synthesis Optimizations For Circuit Designs
Built-In-Self-Test Circuits And Methods In Sectors Of Integrated Circuits
Application:
17/747,808 →
Publication:
US 2022/0277799
Circuits And Methods For Controlling Debugging Firmware In Integrated Circuit Devices
Techniques For Power Management In Compute Circuits
Integrated Circuit with Peek and Poke Protection Circuitry for Multi-Tenant Usage Model
Techniques For Sharing Memory Interface Circuits Between Integrated Circuit Dies
Application:
17/852,093 →
Publication:
US 2022/0334983
Shared Non-Blocking Crossbar Buffer Circuits And Methods
Application:
17/852,859 →
Publication:
US 2022/0326676
Crossbar Circuits And Methods For External Communication With Logic In Integrated Circuits
Application:
17/853,772 →
Publication:
US 2022/0334979
Systems and Methods for Reducing Congestion on Network-On-Chip
Application:
17/854,341 →
Publication:
US 2022/0405453
Chained Command Architecture for Packet Processing
Grid-Based Interconnect System for Modular Integrated Circuit Systems
Application:
17/856,193 →
Publication:
US 2022/0336415
Three-Dimensional Columnar Input-Output (IO) Circuitry for Integrated Circuit Device
Application:
17/856,479 →
Publication:
US 2022/0337250
Multiple Channel Direct Access Memory-Based Configuration System
Application:
17/856,632 →
Publication:
US 2024/0004810
Systems and Methods for Modular Disaggregated Integrated Circuit Systems
Application:
17/856,643 →
Publication:
US 2022/0337251
Dynamic Power Load Line by Configuration
Application:
17/856,776 →
Publication:
US 2022/0335190
Systems and Methods for Programmable Fabric Design Compilation
Application:
17/856,799 →
Publication:
US 2022/0335189
Heterogeneous Timing Closure For Clock-Skew Scheduling or Time Borrowing
Application:
17/856,804 →
Publication:
US 2022/0334609
Multi-Purpose Interface for Configuration Data and User Fabric Data
Concept for Orchestration of Microservices
Application:
17/934,581 →
Publication:
US 2024/0143290
Systems And Methods For Generating A Temperature Dependent Supply Voltage
Application:
17/949,647 →
Publication:
US 2023/0008041
Programmable Input And Output Interfaces In Processing Integrated Circuits For Servers And Other Devices
Application:
17/950,728 →
Publication:
US 2023/0018793
High Performance Systems And Methods For Modular Multiplication
Application:
17/952,085 →
Publication:
US 2023/0026331
Techniques For Booting A Compute Integrated Circuit Using A Boot Management Controller In A Processing Integrated Circuit
Application:
17/954,698 →
Publication:
US 2023/0035058
Die-to-Die Interconnect Architecture for Hardware-Agnostic Modeling
Application:
17/956,372 →
Publication:
US 2023/0042718
Method and Apparatus to Enable CPU Host-Unaware Dynamic FPGA Reconfiguration
Application:
17/956,555 →
Publication:
US 2023/0027807
Retiming and Overclocking of Large Circuits
Application:
17/956,565 →
Publication:
US 2023/0018414
Package Io Escape Routing on a Disaggregated Shoreline
Application:
17/957,204 →
Publication:
US 2023/0028475
Backside Metallization for FPGA Resources
Application:
17/957,210 →
Publication:
US 2023/0024515
Die-to-Die Power Delivery
Application:
17/957,217 →
Publication:
US 2023/0024662
Power Savings by Register Insertion in Large Combinational Circuits
Application:
17/957,235 →
Publication:
US 2023/0027064
Flexible Circuit for Real and Complex Filter Operations
Application:
17/957,339 →
Publication:
US 2024/0113699
Software-Defined Synthesizable Testbench
Application:
17/970,557 →
Publication:
US 2023/0052788
Techniques For Clock Signal Transmission In Integrated Circuits And Interposers
Circuit Systems And Methods Using Spacer Dies
Application:
18/070,361 →
Publication:
US 2023/0100829
Host Managed Memory Shared by Multiple Host Systems in a High Availability System
Application:
18/071,923 →
Publication:
US 2024/0176740
SYSTEMS AND METHODS FOR UCIe-AIB CHIPLET INTERFACE INTEROPERABILITY
Application:
18/075,183 →
Publication:
US 2023/0096585
Techniques For Reducing Filter Distortion In Data Using Emphasis
Application:
18/076,831 →
Publication:
US 2023/0096355
Techniques For Compiling High-Level Inline Code
Application:
18/077,170 →
Publication:
US 2023/0116554
Circuit Implementation on Processing Circuitry
Application:
18/077,187 →
Publication:
US 2023/0108339
Techniques For Synchronous Accesses To Storage Circuits
Application:
18/084,158 →
Publication:
US 2023/0118912
Source Synchronous Partition of an SDRAM Controller Subsystem
Application:
18/085,528 →
Publication:
US 2023/0123826
On-Die Aging Measurements for Dynamic Timing Modeling
Face-To-Face Through-Silicon via Multi-Chip Semiconductor Apparatus with Redistribution Layer Packaging and Methods of Assembling Same
Input Output Banks of a Programmable Logic Device
Application:
18/091,626 →
Publication:
US 2023/0140547
Techniques For Capturing Signals From Logic Circuits At A Logic Analyzer
Application:
18/122,238 →
Publication:
US 2023/0213581
Systems And Methods For Correcting Errors in Code For Circuit Designs
Application:
18/122,612 →
Publication:
US 2023/0222275
Iterative Multiplicative Reduction Circuit
Application:
18/122,656 →
Publication:
US 2023/0273770
Techniques For Replacing Logic Circuits In Modules With Configurable Circuits
Application:
18/124,259 →
Publication:
US 2023/0222274
Embedded Multi-Die Interconnect Bridge with Improved Power Delivery
Application:
18/128,964 →
Publication:
US 2023/0238356
3D Convolutional Neural Network (CNN) Implementation on Systolic Array-Based FPGA Overlay CNN Accelerator
Application:
18/129,341 →
Publication:
US 2023/0237014
Configurable Semiconductor Package Capacitors and Method
Application:
18/129,443 →
Publication:
US 2024/0332222
Pipelined Galois Counter Mode Hash Circuit
Application:
18/129,709 →
Publication:
US 2023/0239136
Fabric Die to Fabric Die Interconnect for Modularized Integrated Circuit Devices
Cross-Coupled Power Multiplexing in High Voltage Applications
Application:
18/140,481 →
Publication:
US 2024/0364333
Systems and Methods for Decomposed Digital Filter
Application:
18/145,002 →
Publication:
US 2023/0128025
System-In-Package Network Processors
Modular Compilation Flows for a Programmable Logic Device
Application:
18/191,785 →
Publication:
US 2023/0237231
Fast Fpga Compilation from Software Flows Through Partial Reconfiguration and Hardened Network-On-Chip
Application:
18/191,789 →
Publication:
US 2023/0237230
Systems And Methods For Verification Of Data Erasure
Application:
18/196,112 →
Publication:
US 2024/0380607
Systems And Methods With Auxiliary Control Boards Having Interface Devices
Systems And Methods For Selecting Decoupling Capacitance Using A Power Jumper Circuit
Application:
18/207,842 →
Publication:
US 2023/0334212
Extended Floating-Point Range Addition and Multiplication
Application:
18/210,630 →
Publication:
US 2023/0367547
Single Instruction, Multiple Thread (Simt) Processors, Methods, Systems, and Instructions
Application:
18/213,257 →
Publication:
US 2023/0333857
Systems And Methods For Load Balancing Memory Traffic
Application:
18/215,732 →
Publication:
US 2023/0342313
Integrated Circuits with Machine Learning Extensions
Application:
18/216,797 →
Publication:
US 2023/0342111
Circuit Systems And Methods For Transmitting Signals Between Devices
Application:
18/216,867 →
Publication:
US 2023/0342309
Efficient Triangular Systolic Array-Based Matrix Inversion
Application:
18/217,011 →
Publication:
US 2023/0342418
Architecture and Testing for an Integrated Circuit Package
Application:
18/217,200 →
Publication:
US 2023/0341463
Apparatus and Method for Graceful Degradation of Redundant Processing
Application:
18/217,349 →
Publication:
US 2025/0004892
Systems And Methods For Debugging Cryptographic Modules
Application:
18/236,737 →
Publication:
US 2023/0393197
Asymmetrical Memory Circuits And Methods
Application:
18/241,217 →
Publication:
US 2023/0410897
Compute-In-Memory Systems and Methods
Innovative Interconnect Design for Package Architecture to Improve Latency
Integrated Circuit Device with Separate Die for Programmable Fabric and Programmable Fabric Support Circuitry
Application:
18/300,330 →
Publication:
US 2023/0253965
Methods and Apparatus for Profile-Guided Optimization of Integrated Circuits
Interface Bridge Between Integrated Circuit Die
Modular Periphery Tile for Integrated Circuit Device
Fast Fpga Compilation Through Bitstream Stitching
Application:
18/338,236 →
Publication:
US 2023/0333826
Methods and Apparatus for Reducing Microbumps for Inter-Die Double-Data Rate (Ddr) Transfer
Techniques For Controlling Access To Provisioning Integrated Circuits
Application:
18/369,612 →
Publication:
US 2024/0005044
Electrostatic Discharge Protection (Esd) Circuitry Including Esd Circuit and Output Driver
Application:
18/372,260 →
Publication:
US 2025/0107246
Digital Signal Processing Circuitry with Multiple Precisions and Dataflows
Application:
18/373,878 →
Publication:
US 2024/0118870
Timing Model for Chip-to-Chip Connection in a Package
Application:
18/375,299 →
Publication:
US 2024/0028815
Efficient Logic Blocks Architectures for Dense Mapping of Multipliers
Application:
18/473,870 →
Publication:
US 2024/0028295
Techniques For Assessing Health Of Configurable Logic Circuits
Application:
18/475,199 →
Publication:
US 2024/0012972
Fast CAD Compilation Through Coarse Macro Lowering
Application:
18/475,512 →
Publication:
US 2024/0020449
Systems And Methods For Thermal Monitoring In Integrated Circuits
Application:
18/476,702 →
Publication:
US 2024/0027279
Inter-Die Communication of Programmable Logic Devices
Application:
18/478,003 →
Publication:
US 2024/0028544
Simultaneous Configuration of Programmable Logic Fabric and Disaggregated Dies
Application:
18/478,537 →
Publication:
US 2025/0111117
Software Assisted Hardware Offloading Cache Using FPGA
Application:
18/478,602 →
Publication:
US 2024/0037037
Coherency Domain Cacheline State Tracking
Application:
18/478,621 →
Publication:
US 2024/0037038
Translation Circuitry for Access Control Identifier Mechanisms
Application:
18/478,661 →
Publication:
US 2024/0056448
Circuits And Methods For Multi-Layered Networks
Application:
18/478,755 →
Publication:
US 2024/0031308
Phase-Change Programmable Vias for Structured ASICs
Application:
60/894,548 →
Forward error correction CODEC
Application:
60/994,314 →
Method for Multiple Lane Distribution (MLD) De-Skew
Application:
61/154,058 →
Strict-Sense Minimal Spanning Switch Non-Blocking Architecture
Application:
61/227,923 →
Metal Oxide Semiconductor Device And Method Of Forming The Same; Three-Dimensional Decoupled Package For Highly Distributed LDMOS Power Switches For Use In Switch-Mode Dc-Dc Power Converters; Three-Dimensional Mixed Pillar Routing For Highly Distributed LDMOS Power Switches For Use In Switch-Mode Power Converters; Semiconductor Device Formed With Plural Metallic Layers
Application:
61/732,208 →
Effective Timing-Driven Detailed Placement Algorithm for FPGAs
Application:
62/406,877 →
High Performance Qr Decomposition Systems and Methods
Application:
62/481,504 →
Convolution Neural Network Formulation Systems and Methods
Application:
62/488,629 →
Statically-Schedulable Feed and Drain Structure for Systolic Array Architecture
Application:
62/488,635 →
Lower Precision Neural Network Systems and Methods
Application:
62/488,636 →
Implementation of Floating-Point Trigonometric Functions in an Integrated Circuit Device
Application:
62/502,127 →
High Radix Subset Code Multiplier Architecture
Application:
62/522,546 →
Reduction Operation Mapping Systems and Methods
Application:
62/532,871 →
Hyperbolic Functions for Machine Learning Acceleration
Application:
62/532,874 →
Hyperbolic Functions for Machine Learning Acceleration
Application:
62/555,510 →
Variable Delay Circuits And Methods
Application:
62/576,276 →
Innovative Interconnect Design for Package Architecture to Improve Latency
Application:
62/577,581 →
On-Device Bitstream Validation
Application:
62/585,522 →
Synthesis for FPGA Embedded Feature Placement
Application:
62/616,929 →
Multi-Input Reduction Structure for Very Large Integers
Application:
62/697,265 →
DDR-T enabled near-memory FPGA compute device in DIMM form-factor
Application:
62/719,911 →
Circuitry for High-Bandwidth, Low-Latency Machine Learning
Application:
62/736,981 →
Geometric Synthesis
Application:
62/814,100 →
High Performance Regularized Network-on-Chip Architecture
Application:
62/820,049 →
Machine Learning Training Architecture for Programmable Devices
Application:
62/824,797 →
FPGA Specialist Processing Block for Artificial Intelligence
Application:
62/948,110 →
Implementing Large Multipliers in Tensor Arrays
Application:
62/948,114 →
Systems and Methods for Loading Weights into a Tensor Processing Block
Application:
62/948,124 →
Folded Integer Multiplication for FPGAs
Application:
63/004,469 →
Soft Network-on-Chip Overlay Through a Partial Reconfiguration Region
Application:
63/044,850 →
Analog-to-Digital Converter or Digital-to-Analog Converter with Deterministic Latency
Application:
63/059,698 →
Vector Processor Architectures
Application:
63/072,095 →
First-In First-Out Buffer with Lookahead Performance Booster
Application:
63/081,134 →
Joint Channel Filtering and Crest Factor Reduction Architecture
Application:
63/134,663 →
Fabric Memory Network-On-Chip
Application:
63/311,028 →
Load Balancing Memory Specific Traffic Optimizer
Application:
63/403,426 →
Integrated Circuit Architecture for a Cryptographic Puzzle Solver
Application:
63/409,201 →
Software-Defined Synthesizable Testbench
Application:
63/409,648 →
Digital Signal Processing Block with Multiple Precisions and Dataflows
Application:
63/414,189 →
Pipelined GCM Hash Circuit
Application:
63/429,115 →
High-Performance Soft General Purpose Graphics Processing Unit (GPGPU)
Application:
63/443,314 →
Related Assignments
(10)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Aug 15, 2013
From: LOTFI, ASHRAF W.; WILKOWSKI, MATHEW A.; LIAKOPOULOS, TRIFON M.; WELD, JOHN D.
To: ENPIRION, INC.
Reel/Frame 031016/0705 →
Assignment of Assignor's Interest
Mar 11, 2019
From: EASIC CORPORATION
To: INTEL CORPORATION
Reel/Frame 048559/0162 →
Assignment of Assignor's Interest
Jun 20, 2022
From: ENPIRION, INC.
To: ALTERA CORPORATION
Reel/Frame 060390/0187 →
Assignment of Assignor's Interest
Aug 11, 2022
From: ALTERA CORPORATION
To: INTEL CORPORATION
Reel/Frame 061159/0694 →
Change of Name
Aug 29, 2022
From: INTEL OF CANADA, LTD.
To: INTEL TECHNOLOGY OF CANADA, LTD.
Reel/Frame 061334/0500 →
Merger and Change of Name
Aug 29, 2022
From: ALTERA CANADA LTD.; INTEL OF CANADA, LTD.
To: INTEL OF CANADA, LTD.
Reel/Frame 060921/0206 →
Change of Name
Aug 29, 2022
From: ALTERA CANADA CO.
To: ALTERA CANADA LTD.
Reel/Frame 061333/0007 →
Assignment of Assignor's Interest
Oct 10, 2022
From: INTEL TECHNOLOGY OF CANADA, ULC
To: INTEL CORPORATION
Reel/Frame 061368/0947 →
Change of Name
Oct 10, 2022
From: INTEL TECHNOLOGY OF CANADA, LTD.
To: INTEL TECHNOLOGY OF CANADA, ULC
Reel/Frame 061359/0223 →
Security Interest
Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →