Seemingly monolithic interface between separate integrated circuit die
A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.
1. An integrated circuit device comprising:
a sampling circuitry to sample a first portion of a plurality of signals more often than a second portion of the plurality of signals; and
a transmitter to generate a serial signal based on the plurality of signals and transmit the serial signal, wherein a frame of the serial signal comprises a first time slot comprising a flag bit indicating a state of a plurality of bits of the first time slot, a first plurality of time slots that comprise the first portion of the plurality of signals, and a second plurality of time slots that comprise the second portion of the plurality of signals.
2. The integrated circuit device of claim 1 , comprising a first die, wherein the first die comprises the sampling circuitry and the transmitter.
3. The integrated circuit device of claim 2 , wherein the first die comprises an interface to store the plurality of signals.
4. The integrated circuit device of claim 2 , wherein:
the first plurality of time slots of the frame comprises a first number of time slots;
the second plurality of time slots of the frame comprises a second number of time slots; and
the first number of time slots is greater than the second number of time slots.
5. The integrated circuit device of claim 2 , comprising a second die, wherein the second die comprises a receiver to receive the serial signal from the first die.
6. The integrated circuit device of claim 5 , wherein the second die comprises:
deserialization circuitry to obtain the plurality of signals based on the serial signal; and
a second interface to store the plurality of signals obtained by the deserialization circuitry.
7. The integrated circuit device of claim 5 , wherein the second die is to communicatively couple the first die to circuitry located external to the integrated circuit device.
8. The integrated circuit device of claim 7 , wherein the first die comprises a processor.
9. The integrated circuit device of claim 7 , comprising a substrate, wherein:
the first die and the second die are mounted on the substrate; and
the substrate comprises interconnect circuitry to communicatively couple the transmitter to the receiver.
10. The integrated circuit device of claim 1 , wherein the first time slot is positioned before the first plurality of time slots or the second plurality of time slots.
11. A system comprising:
a substrate;
a first integrated circuit die mounted on the substrate, the first integrated circuit die comprising:
sampling circuitry to sample a first portion of a plurality of signals more often than a second portion of the plurality of signals; and
a transmitter to generate a serial signal based on the plurality of signals and transmit the serial signal, wherein a frame of the serial signal comprises a first time slot comprising a flag bit to indicate a state of a plurality of bits of the first time slot, a first plurality of time slots that comprise the first portion of the plurality of signals, and a second plurality of time slots that comprise the second portion of the plurality of signals, wherein the first plurality of time slots includes more time slots than the second plurality of time slots; and
a second integrated circuit die mounted on the substrate, the second integrated circuit die comprising a receiver to receive, via the substrate, the serial signal from the first integrated circuit die.
12. The system of claim 11 , wherein the sampling circuitry is to cause the plurality of signals to be sampled according to a first clock over a sampling window that includes a plurality of edges of the first clock, wherein the first portion of the plurality of signals is sampled at least in part by:
detecting a current state of a signal of the first portion of the plurality of signals a defined number of times at edges of the first clock;
latching the signal when the current state is the same for the defined number of times; and
outputting the latched signal into a sampling register.
13. The system of claim 11 , wherein:
the first integrated circuit die comprises a processor; and
the second integrated circuit die is to communicatively couple the processor to circuitry external to the system.
14. The system of claim 11 , wherein the sampling circuitry is to sample the first portion of the plurality of signals at least twice as often as the second portion of the plurality of signals.
15. The system of claim 11 , wherein the second integrated circuit die comprises:
deserialization circuitry to obtain the plurality of signals based on the serial signal; and
a second interface to store the plurality of signals obtained by the deserialization circuitry.
16. The integrated circuit device of claim 11 , wherein the first time slot is positioned before the first plurality of time slots or the second plurality of time slots.
17. A system comprising:
a substrate; and
a first integrated circuit die mounted on the substrate, wherein the first integrated circuit die comprises:
sampling circuitry clocked to a clock, wherein the sampling circuitry is to:
receive a plurality of signals comprising a signal and a second signal;
sample the signal at a first sampling rate to produce a first plurality of sampled signals, wherein the signal is sampled over a sampling window that includes a plurality of edges of the clock, wherein the signal is sampled at least in part by:
detecting a current state of the signal a defined number of times at edges of the clock;
latching the signal when the current state is the same for the defined number of times; and
outputting the latched signal into a sampling register; and
sample the second signal of the plurality of signals at a second sampling rate to produce a second plurality of sampled signals, wherein the first sampling rate is a higher frequency than the second sampling rate;
a transmitter to generate a serial signal based on the plurality of signals transmit the serial signal, wherein a frame of the serial signal comprises:
a first plurality of time slots that comprises the first plurality of sampled signals; and
a second plurality of time slots that comprises the second plurality of sampled signals.
18. The system of claim 17 , comprising a second integrated circuit die mounted on the substrate, wherein the second integrated circuit die comprises a receiver to receive, via the substrate, the serial signal.
19. The system of claim 18 , wherein:
the first integrated circuit die comprises a processor; and
the second integrated circuit die is to communicatively couple the processor to circuitry external to the system.
20. The system of claim 18 , wherein the second integrated circuit die comprises:
deserialization circuitry to obtain the plurality of signals based on the serial signal; and
a second interface to store the plurality of signals obtained by the deserialization circuitry.