Side-channel attack resistant fuse programming
The disclosed systems and methods may secure the fuse programming process in programmable devices to reduce or eliminate malicious discovery of data (e.g., the encryption key, the configuration bitstream) stored in nonvolatile memory via side-channel attacks. A processor may generate a randomized fuse list and the fuses may be blown in the randomized order. Additionally or alternatively, the processor may randomize the wait time between programming of each fuse. Further, the processor may generate a simplified fuse list including only fuses to be blown. The disclosed security systems and methods may be used individually or in combination to prevent determination of sensitive data, such as the encryption key, by monitoring, for example, power consumption in side-channel attacks.
1. A method for securely programming a plurality of fuses of a programmable logic device, comprising:
receiving, via a processor communicatively coupled to the programmable logic device, data to be programmed in a set of fuses of the plurality of fuses;
generating, via the processor, a shuffled sequence of the plurality of fuses;
determining, via the processor, a variable amount of time between programming a first fuse of the set of fuses and a second fuse of the set of fuses; and
programming, via the processor, the set of fuses of the plurality of fuses with the data according to the shuffled sequence by programming the second fuse after the variable amount of time has elapsed from programming the first fuse.
2. The method of claim 1 , wherein the data comprises an encryption key.
3. The method of claim 1 , comprising:
receiving, via the processor, an encrypted configuration bitstream configured to configure a programmable fabric of the programmable logic device; and
programming, via the processor, the programmable fabric based at least in part on the encrypted configuration bitstream.
4. The method of claim 3 , comprising decrypting, via the processor, the encrypted configuration bitstream using the data programmed in the set of fuses.
5. The method of claim 3 , wherein programming, via the processor, the programmable fabric based at least in part on the encrypted configuration bitstream comprises decrypting, via the processor, the encrypted configuration bitstream using the data programmed in the set of fuses.
6. The method of claim 1 , wherein the shuffled sequence of the plurality of fuses is generated by a Fisher-Yates shuffle algorithm.
7. The method of claim 1 , wherein the shuffled sequence is generated by a shuffle algorithm based at least in part on a random number generator.
8. The method of claim 1 , wherein the shuffled sequence is generated by a shuffle algorithm based at least in part on a pseudorandom number generator.
9. The method of claim 1 , comprises selecting, via the processor, one or more fuses of the set of fuses based at least in part on a memory location offset.
10. The method of claim 1 , comprising removing, via the processor, one or more fuses from the shuffled sequence of the plurality of fuses when the one or more fuses already hold the data to be programmed.
11. A system for securely programming a plurality of fuses of a programmable logic device, comprising:
a processor configured to determine a variable amount of time; and
a programmable logic device communicatively coupled to the processor, wherein the programmable logic device comprises the plurality of fuses configured to:
receive a plurality of bits of data to be programmed in the plurality of fuses;
store a first bit of data of the plurality of bits of data in a first fuse; and
store a second bit of data in a second fuse when the variable amount of time has elapsed since storing the first bit of data in the first fuse.
12. The system of claim 11 , wherein the programmable logic device comprises a field programmable gate array (FPGA) device.
13. The system of claim 11 , wherein the processor is configured to determine the variable amount of time by using a random number generator or a pseudorandom number generator.
14. The system of claim 11 , wherein the processor is configured to generate a shuffled sequence of the plurality of fuses upon receiving the plurality of bits of data; and remove one or more fuses of the plurality of fuses from the shuffled sequence when the one or more fuses already hold the data to be programmed.
15. The system of claim 14 , wherein the first fuse immediately precedes the second fuse.
16. A tangible, non-transitory, computer readable medium storing instructions for securely programming a plurality of fuses of a programmable logic device, comprising instructions to cause a processor communicatively coupled to the programmable logic device to:
receive data to be programmed in a set of fuses of the plurality of fuses;
generate a sequence of the plurality of fuses;
remove fuses from the sequence that are not included in the set of fuses;
determine a variable amount of time to wait between programming a first fuse of the set of fuses and a second fuse of the set of fuses; and
program the set of fuses with the data by programming the second fuse after the variable amount of time has elapsed from programming the first fuse.
17. The tangible, non-transitory, computer readable medium of claim 16 , wherein the sequence comprises a shuffled sequence, wherein the instructions cause the processor to program the set of fuses with the data according to the shuffled sequence.
18. The tangible, non-transitory, computer readable medium of claim 17 , wherein the shuffled sequence is generated by a shuffle algorithm based at least in part on a random number generator or a pseudorandom number generator.
19. The tangible, non-transitory, computer readable medium of claim 16 , wherein the instructions cause the processor to determine the variable amount of time by using a random number generator.
20. The tangible, non-transitory, computer readable medium of claim 16 , wherein the instructions cause the processor to determine the variable amount of time by using a pseudorandom number generator.