SECURITY ON DIE-TO-DIE INTERCONNECT
Systems or methods of the present disclosure may provide a semiconductor device including a die of a multi-die package including encryption circuitry to receive data and to encrypt the data to generate encrypted data; and a connection interface to transmit the encrypted data over a die-to-die interconnect to a second die.
1 . A semiconductor device comprising:
a multi-die package comprising:
a first die comprising:
first encryption circuitry to receive data and to encrypt the data to generate encrypted data; and
a first connection interface to transmit the encrypted data over a die-to-die interconnect;
the die-to-die interconnect; and
a second die comprising:
a second connection interface to receive the encrypted data from the first die via the die-to-die interconnect; and
second encryption circuitry to receive the encrypted data and to decrypt the encrypted data to generate decrypted data.
2 . The semiconductor device of claim 1 , wherein the second encryption circuitry is to receive additional data and to encrypt the additional data to generate additional encrypted data.
3 . The semiconductor device of claim 2 , wherein the second connection interface is to transmit the additional encrypted data.
4 . The semiconductor device of claim 3 , wherein the first connection interface is to receive the additional encrypted data over the die-to-die interconnect.
5 . The semiconductor device of claim 4 , wherein the first encryption circuitry is to decrypt the additional encrypted data to generate additional decrypted data.
6 . The semiconductor device of claim 1 , wherein the second die comprises data utilization circuitry to use the decrypted data.
7 . The semiconductor device of claim 6 , wherein the data utilization circuitry comprises a processor or a field-programmable gate array.
8 . The semiconductor device of claim 1 , wherein the first encryption circuitry does not encrypt at least some subsequent data transmitted from the first die over the die-to-die interconnect.
9 . The semiconductor device of claim 8 , wherein the first encryption circuitry is to encrypt the encrypted data and to not encrypt the at least some subsequent data based on a control signal.
10 . The semiconductor device of claim 9 , wherein the control signal is based at least in part on respective values for a user flag in the data and the at least some subsequent data.
11 . The semiconductor device of claim 8 , wherein the first die comprises bypass circuitry to cause the at least some subsequent data to bypass the first encryption circuitry.
12 . The semiconductor device of claim 1 , wherein the first connection interface comprises a first plurality of channels, and wherein the second connection interface comprises a second plurality of channels.
13 . The semiconductor device of claim 12 , wherein at least one or more channels of the first plurality of channels comprise encryption circuitry to encrypt data, decrypt data, or both.
14 . The semiconductor device of claim 13 , wherein encryption or decryption operations of the one or more channels of the first plurality of channels are driven independently of each other.
15 . The semiconductor device of claim 1 , wherein a clock frequency of encryption is a fraction of a frequency of unencrypted data transfer.
16 . A semiconductor device comprising:
a die of a multi-die package comprising:
encryption circuitry to receive data and to encrypt the data to generate encrypted data; and
a connection interface to transmit the encrypted data over a die-to-die interconnect to a second die within the multi-die package.
17 . The semiconductor device of claim 16 , wherein the encryption circuitry is to encrypt the data based on metadata of a packet of the data.
18 . The semiconductor device of claim 16 , wherein the connection interface comprises a plurality of channels, and wherein the encrypted data is transmitted over the die-to-die interconnect by one of the plurality of channels, and wherein unencrypted data is transmitted over the die-to-die interconnect by a remainder of the plurality of channels.
19 . A semiconductor device comprising:
a die of a multi-die package comprising:
a connection interface to receive encrypted data from a second die of the multi-die package via a die-to-die interconnect;
decryption circuitry to receive the encrypted data and to decrypt the encrypted data to generate decrypted data; and
data utilization circuitry to utilize the decrypted data.
20 . The semiconductor device of claim 19 , wherein the data utilization circuitry comprises a processor to receive the decrypted data from the decryption circuitry.