Systems and methods for aligning received data
The present application is directed to an electronic device that includes a receiver configured to receive data from a second electronic device. The data includes a plurality of blocks, and each block of the plurality of blocks comprises a sync header. The receiver is also configured to align the data by performing 2 to 1 multiplexing and output the aligned data.
1. An electronic device comprising:
a receiver comprising:
gearbox circuitry comprising a data buffer, wherein the gearbox circuitry is configured to:
receive data from a second electronic device, wherein the data comprises a plurality of blocks, wherein each block of the plurality of blocks comprises a sync header; and
store a portion of the data in a particular configuration in the data buffer; and
sync header detection and alignment circuitry comprising multiplexer circuitry, wherein the sync header detection and alignment circuitry is configured to:
determine a location of the sync header;
determine an adjustment to be made based on the location of the sync header; and
provide an indication of the adjustment to the gearbox circuitry; and
align the data by performing 2 to 1 multiplexing via the multiplexer circuitry; and
output the aligned data.
2. The electronic device of claim 1 , wherein the gearbox circuitry is configured to store the portion of the data in the particular configuration based on the indication of the adjustment.
3. The electronic device of claim 1 , wherein the gearbox circuitry is configured to output semi-aligned data comprising at least one complete sync header.
4. The electronic device of claim 3 , wherein the sync header detection and alignment circuitry comprises the multiplexer circuitry configured to:
receive the semi-aligned data; and
generate the aligned data by performing the 2 to 1 multiplexing.
5. The electronic device of claim 4 , wherein:
the sync header detection and alignment circuitry comprises a data register configured to store a portion of previous data; and
the multiplexer circuitry receives the portion of the previous data.
6. The electronic device of claim 5 , wherein the aligned data comprises the portion of the previous data.
7. The electronic device of claim 5 , wherein the data register is configured to store only a single bit of data.
8. The electronic device of claim 1 , wherein the electronic device comprises a programmable logic device.
9. The electronic device of claim 8 , wherein the programmable logic device comprises a field-programmable gate array (FPGA) or an application specific integrated circuit (ASIC).
10. The electronic device of claim 1 , wherein the multiplexer circuitry is configured to:
determine a configuration of the data based on a registered bit of the data; and
align the data based on the configuration.
11. The electronic device of claim 1 , wherein the multiplexer circuitry is configured to receive two bits of the data and output one bit of the data.
12. The electronic device of claim 1 , wherein the aligned data comprises the sync header in a same bit position at each block of the plurality of blocks.
13. The electronic device of claim 1 , wherein the multiplexer circuitry is configured to receive 133 bits of the data and output 132 bits of the aligned data.