Methods and apparatus for performing timing driven hardware emulation
View Patent ↗Programmable integrated circuits may be used to perform hardware emulation of an application-specific integrated circuit (ASIC) design. The ASIC design may be loaded onto the programmable integrated circuit. During hardware emulation operations, an emulation host may be used to coordinate testing of the DUT on the programmable device. Circuit design tools may be used to extract parasitics from the ASIC design, compute low-level interconnect delays, convert the interconnect delays to higher-level port-to-port delays, convert the port-to-port delays to timing constraints, and generate corresponding configuration data for programming the programmable integrated circuit to emulate the ASIC design. The programmable integrated circuit may then be tested for functional and performance integrity.
1. A method of implementing an integrated circuit using circuit design tools, the method comprising:
generating a first circuit design having a target operating frequency;
generating frequency-dependent timing constraints based on the first circuit design; and
generating, based on the frequency-dependent timing constraints, a second circuit design having a maximum achievable operating frequency less than the target operating frequency, wherein the second circuit design emulates the first circuit design on the integrated circuit and wherein the frequency-dependent timing constraints are a function of a ratio of the target operating frequency and the maximum achievable operating frequency.
2. The method of claim 1 , wherein the first circuit design is an application-specific integrated circuit (ASIC) design.
3. The method of claim 2 , further comprising:
generating configuration data based on the second circuit design; and
loading the configuration data into the integrated circuit.
4. The method of claim 1 , further comprising:
extracting parasitics from the first circuit design; and
computing point-to-point interconnect delays using the extracted parasitics.
5. The method of claim 4 , further comprising:
converting the point-to-point interconnect delays to port-to-port delays; and
converting the port-to-port delays to the timing constraints.
6. The method of claim 1 , further comprising:
running functional tests on the integrated circuit to verify that the first circuit design satisfies design criteria.
7. The method of claim 1 , further comprising:
loading a test operating system into the integrated circuit to verify that the test operating system satisfies design criteria.
8. A non-transitory computer-readable storage medium comprising instructions for:
generating an application-specific integrated circuit (ASIC) design;
generating timing information associated with the ASIC design by generating a layout of the ASIC design, extracting parasitics from the layout, computing a first type of delay based on the extracted parasitics, and converting the first type of delay to a second type of delay that is different than the first type of delay; and
generating an emulation design using the timing information.
9. The non-transitory computer-readable storage medium of claim 8 , wherein the instructions for generating the timing information further comprises instructions for converting the second type of delay into frequency-dependent timing constraints.
10. The non-transitory computer-readable storage medium of claim 8 , further comprising instructions for:
implementing the emulation design on a programmable integrated circuit to verify that the ASIC design satisfies design criteria.
11. A programmable integrated circuit, comprising:
programmable logic circuitry configured using a programmable logic design that is generated using an application-specific integrated circuit (ASIC) design and timing constraints of the ASIC design, wherein the programmable logic design emulates the ASIC design on the programmable integrated circuit.
12. The programmable integrated circuit of claim 11 , wherein the timing constraints comprises frequency-dependent timing constraints.
13. The programmable integrated circuit of claim 12 , wherein the ASIC design has a target operating frequency, wherein the programmable logic design has a maximum achievable operating frequency that is less than the target operating frequency, and wherein the frequency-dependent timing constraints are a function of the ratio of the target operating frequency to the maximum achievable operating frequency.
14. The programmable integrated circuit of claim 13 , wherein the timing constraints are computed based on parasitics extracted from the ASIC design, a first type of delay computed from the extracted parasitics, and a second type of delay that is converted from the first type of delay.
15. The programmable integrated circuit of claim 11 , wherein the programmable logic circuitry is further configured using a test operating system to determine whether the test operating system is compatible with the ASIC design.
16. The programmable integrated circuit of claim 11 , wherein the programmable logic circuitry comprises field-programmable gate array circuitry.