High resolution and low power interpolator for delay chain

1. A delay-locked loop comprising:

a plurality of inverters coupled together, wherein the plurality of inverters receives an input clock signal and outputs a first clock signal and a second clock signal, wherein:

the input clock signal passes through a first set of inverters of the plurality of inverters having a first number of inverters to generate the first clock signal; and

the input clock signal passes through a second set of inverters of the plurality of inverters having a second number of inverters one inverter greater than the first number of inverters to generate the second clock signal;

a polarity matching block that receives the first clock signal and the second clock signal and changes polarity of one of the first clock signal and the second clock signal; and

a slew rate control block that increases interpolation accuracy of the first clock signal and the second clock signal.

2. The delay-locked loop of claim 1 , comprising a decoder that decodes a coarse delay code that enables the first set of inverters and the second set of inverters.

3. The delay-locked loop of claim 1 , wherein the polarity matching block comprises an inverter and a component that mimics delay of the inverter.

4. The delay-locked loop of claim 3 , wherein the component comprises a transmission gate.

5. The delay-locked loop of claim 1 , comprising a phase interpolator that interpolates between the first clock signal and the second clock signal.

6. The delay-locked loop of claim 5 , wherein the phase interpolator comprises a plurality of interpolator cells each comprising a respective plurality of the inverters.

7. The delay-locked loop of claim 6 , wherein the phase interpolator decodes a fine delay code that enables one or more interpolator cells of the plurality of interpolator cells.

8. An integrated circuit comprising:

a delay chain that delays an input clock signal, comprising:

a plurality of inverters coupled together that receives the input clock signal and outputs a first clock signal and a second clock signal, wherein:

the input clock signal passes through a first set of inverters of the plurality of inverters having a first number of inverters to generate the first clock signal; and

the input clock signal passes through a second set of inverters of the plurality of inverters having a second number of inverters one inverter greater than the first number of inverters to generate the second clock signal; and

a polarity matching block that receives the first clock signal and the second clock signal and changes polarity of one of the first clock signal and the second clock signal; and

a controller communicatively coupled to the delay chain that:

receives the input clock signal and a feedback clock signal from a clock distribution network; and

instructs the delay chain to delay the input clock signal such that a first phase of the input clock signal approximately matches a second phase of the feedback clock signal at least in part by sending an instruction sequence of bits to the delay chain, wherein the instruction sequence of bits comprises a coarse delay code and a fine delay code.

9. The integrated circuit of claim 8 , wherein the delay chain comprises a decoder communicatively coupled to the plurality of inverters that decodes the coarse delay code.

10. The integrated circuit of claim 9 , wherein the delay chain enables the first set of inverters and the second set of inverters based on the coarse delay code.

11. The integrated circuit of claim 8 , wherein the delay chain comprises a phase interpolator that interpolates between the first clock signal and the second clock signal, wherein the phase interpolator comprises a plurality of interpolator cells each comprising a respective plurality of inverters.

12. The integrated circuit of claim 11 , wherein the phase interpolator decodes the fine delay code and enables one or more interpolator cells of the plurality of interpolator cells.

13. The integrated circuit of claim 11 , wherein the phase interpolator interpolates between the first clock signal and the second clock signal after the polarity matching block changes polarity of the one of the first clock signal and the second clock signal.

14. The integrated circuit of claim 11 , wherein the plurality of interpolator cells are connected in parallel.

15. The integrated circuit of claim 11 , wherein the plurality of interpolator cells are connected in series.

16. The integrated circuit of claim 8 , wherein the delay chain comprises slew rate control circuits that increase interpolation accuracy of the first clock signal and the second clock signal.

17. A method for delay an input clock signal, comprising:

receiving the input clock signal;

instructing a delay chain to send the input clock signal through a first set of inverters of the delay chain having a first number of inverters to generate a first clock signal;

instructing the delay chain to send the input clock signal through a second set of inverters of the delay chain having a second number of inverters one inverter greater than the first number of inverters to generate a second clock signal;

instructing a polarity matching block to change polarity of the first clock signal or the second clock signal; and

instructing a phase interpolator to interpolate between the first clock signal and the second clock signal; and

instructing a slew rate control block to increase interpolation accuracy of the first clock signal and the second clock signal.

18. The method of claim 17 , wherein instructing the phase interpolator to interpolate between the first clock signal and the second clock signal occurs after instructing the delay chain to send the input clock signal through the first set of inverters and instructing the delay chain to send the input clock signal through the second set of inverters.