Debug trace microsectors
Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.
1. An integrated circuit, comprising:
a first network-on-chip disposed around at least a partial perimeter of a plurality of microsectors arranged in a row and column grid; and
a first microsector of the plurality of microsectors, wherein the first microsector is coupled to a first row controller, the first microsector comprising:
a plurality of logic access blocks, each logic access block coupled to a respective one of a plurality of data registers;
a plurality of routing blocks, each routing block comprising a first highly pipelined (HIPI) register chain and a second HIPI register chain, wherein at least one of the plurality of data registers is coupled to at least one of the first HIPI register chain and second HIPI register chain; and
a control block comprising a first shift register chain configurable to shift data out of the first microsector to the first row controller and a second shift register chain configurable to shift data into the first microsector from the first row controller.
2. The integrated circuit of claim 1 , wherein the first shift register chain comprises a plurality of shift registers.
3. The integrated circuit of claim 2 , wherein a portion of the plurality of shift registers are inactive shift registers.
4. The integrated circuit of claim 1 , wherein the first row controller comprises a first control circuit configurable to receive data from the first shift register chain.
5. The integrated circuit of claim 4 , wherein the first row controller comprises a second control circuit configurable to shift data to the second shift register chain.
6. The integrated circuit of claim 5 , wherein the second control circuit is configurable to convert data into a number of data frames.
7. The integrated circuit of claim 4 , wherein the first control circuit is configurable to convert data received from the first shift register chain from a number of data frames to a data format associated with the first row controller.
8. The integrated circuit of claim 1 , wherein a number of bits shifted out from the first shift register chain is based on a frequency of at least one of the plurality of data registers and a frequency of the first shift register chain.
9. A system, comprising:
programmable logic circuitry comprising configuration memory, the programmable logic circuitry comprising:
a first microsector, wherein the first microsector is coupled to a first row controller, the first microsector comprising:
a plurality of logic access blocks, each logic access block coupled to a respective one of a plurality of data registers;
a plurality of routing blocks, each routing block comprising a first highly pipelined (HIPI) register chain and a second HIPI register chain, wherein at least one of the plurality of data registers is coupled to at least one of the first HIPI register chain and the second HIPI register chain; and
a control block comprising a first shift register chain configurable to shift data out of the first microsector to the first row controller; and
a first control circuitry of the first row controller, wherein the first control circuitry is configured to receive data from the first shift register chain.
10. The system of claim 9 , the control block comprising second shift register chain configurable to shift data into the first microsector from the first row controller.
11. The system of claim 10 , comprising a second control circuitry, wherein the second control circuitry is configured to shift data into the second shift register chain.
12. The system of claim 11 , wherein the first control circuitry and the second control circuitry are disposed in the first row controller.
13. The system of claim 11 , wherein the second control circuitry is configured to convert data into a number of data frames.