Methods for determining resistive-capacitive component design targets for radio-frequency circuitry
A methodology for defining resistance-capacitance (RC) design targets based on radio-frequency (RF) simulation is provided. In particular, the method may involve first determining capacitance targets and then determining resistance targets. To compute the capacitance targets, integrate circuit design and simulations tools may run transient analysis to identify critical nodes, perform small signal and sensitivity analysis for the capacitance on the critical nodes, revise original RF specifications by allocating additional margin, and perform interpolation among multiple capacitance values to obtain capacitive design targets that meet the revised specifications. To compute the resistance targets, the circuit design tools may identify critical transistors, run single-pass and DC operating point simulation to determine initial resistance values for the critical transistors, simplify parallel resistive networks, perform sensitivity analysis on the simplified networks, and perform interpolation among multiple resistive values to obtain resistive design targets meet the original RF performance specifications.
1. A method for using circuit design tools to implement an integrated circuit, comprising:
determining target capacitance values by selectively performing sensitivity analysis on only a subset of capacitances on the integrated circuit;
determining target resistance values by selectively performing sensitivity analysis on only a subset of resistances on the integrated circuit, wherein determining the target resistive values comprises performing sensitivity analysis to identify critical transistors on the integrated circuit; and
generating a design for the integrated circuit based on the target capacitance values and the target resistance values and configuring the integrated circuit with the design.
2. The method of claim 1 , wherein determining the target capacitance and resistance values comprises performing radio-frequency (RF) simulation.
3. The method of claim 1 , wherein determining the target capacitance values comprises performing transient analysis to identify non-stationary nodes.
4. The method of claim 3 , wherein determining the target capacitance values further comprises performing sensitivity analysis to generate regression and correlation coefficients.
5. The method of claim 4 , wherein determining the target capacitance values further comprises revising original performance specifications by allocating additional margin.
6. The method of claim 5 , wherein determining the target capacitance values further comprises performing interpolation to compute the target capacitance values that satisfy the revised performance specifications.
7. The method of claim 1 , wherein determining the target resistive values further comprises performing single-pass simulation and DC operating point simulation to obtain initial drain, gate, and source resistance values for the critical transistors.
8. The method of claim 7 , wherein determining the target resistive values further comprises simplifying resistive networks by combining equivalent pull-up, pull-down, and push-pull resistances.
9. The method of claim 8 , wherein determining the target resistive values further comprising performing additional sensitivity analysis on the simplified resistive networks to generate regression and correlation coefficients.
10. The method of claim 9 , wherein determining the target resistance values further comprises performing interpolation to compute the target resistance values that satisfy original performance specifications.
11. A method of using simulation tools running on circuit design computing equipment to implement an integrated circuit, comprising:
obtaining initial parasitic component values;
gathering radio-frequency measurement data on the integrated circuit;
computing an interpolation step size based on the radio-frequency measurement data;
performing sensitivity analysis to generate regression coefficients, wherein the regression coefficients are used to compute the interpolation step size;
performing interpolation using the initial parasitic component values and the computed interpolation step size to obtain desired target parasitic component values; and
generating a design for the integrated circuit based on the target parasitic component values and configuring the integrated circuit with the design.
12. The method of claim 11 , wherein obtaining the initial parasitic component values comprises obtaining a selected one of initial capacitance values and initial resistance values.
13. The method of claim 11 , further comprising:
performing sensitivity analysis to generate correlation coefficients; and
identifying critical capacitive nodes that affect radio-frequency performance of the integrated circuit by comparing the correlation coefficients to a predetermined threshold.
14. The method of claim 11 , further comprising:
identifying critical transistors that affect radio-frequency performance of the integrated circuit.
15. A method of using computer-aided design tools implemented on computer equipment to design an integrated circuit, the method comprising:
identifying non-stationary nodes in the integrated circuit;
performing sensitivity analysis to determine the non-stationary nodes' sensitivity to additional capacitance;
performing interpolation using results from the sensitivity analysis to obtain target capacitance values for the integrated circuit; and
generating a design for the integrated circuit based on the target capacitance values and configuring the integrated circuit with the design.
16. The method of claim 15 , wherein performing the sensitivity analysis comprises generating regression and correlation coefficient values for the additional capacitance.
17. The method of claim 16 , further comprising:
performing additional sensitivity analysis to obtain regression coefficient values; and
performing interpolation using the initial resistance values and the regression coefficients to obtain target resistance values for the integrated circuit.
18. The method of claim 15 , further comprising:
in response to obtaining the target capacitance values, identifying critical transistors in the integrated circuit; and
computing initial resistance values associated with the critical transistors.
19. The method of claim 15 , wherein performing interpolation using the results from the sensitivity analysis comprises:
obtaining a first set of radio-frequency measurement data;
obtaining a second set of radio-frequency measurement data; and
interpolating between the first and second sets of radio-frequency data to obtain at least one of the target capacitance values.