Modular Compilation Flows for a Programmable Logic Device
Systems or methods of the present disclosure may provide an electronic device that includes memory storing instructions; and a processor, that when executing the instructions, is to receive a design for a programmable fabric of an integrated circuit device. The instructions are also to cause the processor to cause compilation of the design into a configuration during a compilation window. The instructions further are to cause the processor to determine at least some routing for the configuration outside of the compilation window.
1 . An electronic device, comprising:
memory storing instructions; and
a processor, that when executing the instructions, is to:
receive a design for a programmable fabric of an integrated circuit device;
cause compilation of the design into a configuration during a compilation window; and
determine at least some routing for the configuration outside of the compilation window.
2 . The electronic device of claim 1 , wherein determining the at least some routing for the configuration comprises compiling the at least some routing before compiling the design in the compilation window.
3 . The electronic device of claim 1 , wherein the at least some routing comprises external routing connecting a region with circuitry outside of the region.
4 . The electronic device of claim 1 , wherein causing compilation of the design during the compilation window comprises compiling intra-region routes.
5 . The electronic device of claim 4 , wherein the intra-region routes comprise routes between processing elements of the programmable fabric or within processing elements of the programmable fabric.
6 . The electronic device of claim 1 , wherein the at least some routing comprises native multiplexers of the programmable fabric.
7 . The electronic device of claim 1 , wherein determining the at least some routing comprises adding or modifying routing after the compilation window.
8 . The electronic device of claim 7 , wherein adding or modifying routing comprises using an engineering change order.
9 . A method, comprising:
receiving a design for a programmable fabric of an integrated circuit device;
compiling the design with at least some routing for an implementation of the design not being compiled with the rest of the design;
determining to add or modify a route of the at least some routing;
changing the route; and
utilizing the design to configure the programmable fabric to perform a function using the changed route.
10 . The method of claim 9 , wherein the at least some routing for the implementation of the design comprises default pre-configured routes.
11 . The method of claim 9 , wherein the at least some routing comprises no external routes extending outside of a region until after compilation of the design.
12 . The method of claim 9 , wherein changing the route includes removing the route, adding an additional route, replacing the route, or combination thereof.
13 . The method of claim 9 , comprising saving the changed route to a library.
14 . The method of claim 13 , wherein determining whether to add or modify the route comprises prioritizing using routes that are pre-compiled over routes that are yet to be compiled.
15 . An electronic device, comprising:
memory storing instructions and a plurality of routing layers each indicating one or more pre-compiled routes available for use in a design; and
a processor, that when executing the instructions, is to:
receive the design for a programmable fabric of an integrated circuit device;
compile the design with local routing within a region during a compilation window;
receive an indication of one or more of the plurality of routing layers;
merge the one or more of the plurality of routing layers with the design with local routing to generate a configuration bitstream; and
utilize the configuration bitstream to configure the programmable fabric of the integrated circuit device.
16 . The electronic device of claim 15 , wherein the instructions are part of design software stored in the memory and implemented by the processor.
17 . The electronic device of claim 15 , wherein a routing layer of plurality of routing layers comprises a single route for the region.
18 . The electronic device of claim 17 , wherein the instructions, when executed, are to cause the processor to merge the one or more of the plurality of routing layers into a composite routing layer before merging the one or more of the plurality of routing layers with the design with local routing.
19 . The electronic device of claim 15 , wherein a routing layer of the plurality of routing layers comprises multiple routes indicated in the routing layer.
20 . The electronic device of claim 15 , wherein the local routing comprises between processing elements of the region or within a processing element of the region, and the pre-compiled routes extend to a boundary of the region.