Software Assisted Hardware Offloading Cache Using FPGA
Circuitry, systems, and methods are provided for an integrated circuit device including a memory storing a data structure, a cache storing a portion of the structure data, and an acceleration function unit providing hardware acceleration for a host device. The acceleration function unit may provide the hardware acceleration by intercepting a request from the host device to access the memory, where the request comprises an address corresponding to a data node of the data structure, identifying a next data node based at least in part on decoding the data node, and loading the next data node into the cache for access by the host device.
1 . An integrated circuit device, comprising:
a memory configurable to store a data structure;
a cache configurable to store a portion of the structure data; and
an acceleration function unit configurable to provide hardware acceleration for a host device by:
intercepting a request from the host device to access the memory, wherein the request comprises an address corresponding to a data node of the data structure;
identifying a next data node based at least in part on decoding the data node; and
loading the next data node into the cache for access by the host device before the host device calls for the next data node.
2 . The integrated circuit device of claim 1 , wherein the acceleration function unit is configured to identify the data structure based on the request and load the data structure into the cache.
3 . The integrated circuit device of claim 1 , wherein the acceleration function unit is configurable with register-transfer logic comprising a type of the data structure stored in the memory, a start address of the data structure, a size of the data structure, or a combination thereof.
4 . The integrated circuit device of claim 3 , wherein the acceleration function unit is configurable to identify the next data node by determining the address is between the start address and the size of the data structure.
5 . The integrated circuit device of claim 1 , wherein the data node comprises a memory pointer to the next data node.
6 . The integrated circuit device of claim 5 , wherein the acceleration function unit is configurable to load the next data node into the cache by:
generating a read request based on the memory pointer in response to identifying the next data node; and
transmitting the read request to the memory to retrieve the next data node.
7 . The integrated circuit device of claim 1 , wherein the acceleration function unit comprises a programmable logic device having a programmable fabric.
8 . The integrated circuit device of claim 7 , wherein the programmable logic device comprises a plurality of acceleration function units comprising the acceleration function unit, and wherein each of the plurality of acceleration function units is configurable to provide the hardware acceleration for a plurality of host devices comprising the host device.
9 . The integrated circuit device of claim 1 , wherein the acceleration function unit is positioned on a memory bus coupling the host device and the memory.
10 . The integrated circuit device of claim 1 , comprising a compute express link type 2 device that exposes the memory to the host device using compute express link memory operations.
11 . An integrated circuit device, comprising:
a programmable logic device, comprising:
an acceleration function unit to provide hardware acceleration for a host device; and
a memory to store a data structure; and
a cache coherency bridge accessible to the host device and configurable to resolve coherency with a host cache of the host device, wherein the acceleration function unit is configurable to prefill the cache coherency bridge with a portion of the data structure based on a memory access request transmitted by the host device.
12 . The integrated circuit device of claim 11 , wherein the acceleration function unit is configurable to:
identify a data node of the data structure corresponding to the memory access request; and
identify a next data node of the data structure that is linked to the data node based at least in part by decoding the data node.
13 . The integrated circuit device of claim 12 , wherein the acceleration function unit is configurable to prefill the cache coherency bridge by:
transmitting a request to the memory comprising the next data node; and
loading the next data node into the cache coherency bridge for access by the host device.
14 . The integrated circuit device of claim 12 , wherein identifying the next data node comprises identifying a memory pointer of the data node, wherein the memory pointer comprise an address of the next data node.
15 . The integrated circuit device of claim 12 , wherein identifying the next data node comprises identifying a next node pointer of the data node, wherein the next node pointer comprises a start signature of the next data node.
16 . The integrated circuit device of claim 11 , wherein the acceleration function unit is configurable based on logic comprising a type of the data structure stored in the memory, a start address of the data structure, a size of the data structure, or a combination thereof.
17 . The integrated circuit device of claim 11 , wherein the data structure comprises a single linked list, a double linked list, a graph, a map, or a tree.
18 . The integrated circuit device of claim 11 , comprising a compute express link type 2 device that exposes the memory to the host device using compute express link memory operations.
19 . A programmable logic device, comprising:
a cache coherency bridge comprising a device cache that the cache coherency bridge is to maintain coherency with a host cache of a host device using a communication protocol with the host device over a link; and
an acceleration function unit to provide a hardware acceleration function for the host device and comprising:
logic circuitry to implement the hardware acceleration function in a programmable fabric of the acceleration function unit; and
a memory that is exposed to the host device as host-managed device memory to be used in the hardware acceleration function,
wherein the logic circuitry is configurable to implement the hardware acceleration function by:
snooping on a first request from the host device indicative of accessing the memory;
identifying a first data node of a data structure corresponding to the first request;
identifying a second data node of the data structure based at least in part by decoding the first data node;
transmitting a second request to the memory comprising an address of the second data node; and
loading the second data node into the cache coherency bridge for access by the host device.
20 . The programmable logic device of claim 19 , wherein the acceleration function unit is configurable based on register-transfer logic comprising a type of the data structure stored in the memory, a start address of the data structure, a size of the data structure, or a combination thereof.