Circuits and methods for configurable scan chains

1. An integrated circuit comprising:

first and second data storage circuits;

first, second, and third shadow storage circuits;

a first multiplexer circuit configurable to provide a state of a first data signal from the first data storage circuit to the first shadow storage circuit in a first snapshot mode;

a second multiplexer circuit coupled between an output of the second data storage circuit and an input of the second shadow storage circuit; and

a third multiplexer circuit coupled to the second multiplexer circuit, wherein the third multiplexer circuit is configurable to provide a state of an output signal of the first shadow storage circuit to an input of the third shadow storage circuit in a scan mode bypassing the second shadow storage circuit.

2. The integrated circuit of claim 1 , wherein the second multiplexer circuit is configurable to provide a second data signal from the second data storage circuit to the second shadow storage circuit in a second snapshot mode.

3. The integrated circuit of claim 1 , wherein the first multiplexer circuit provides a scan signal to the first shadow storage circuit in the scan mode.

4. The integrated circuit of claim 1 further comprising:

a third data storage circuit; and

a fourth multiplexer circuit configurable to provide a state of a second data signal from the third data storage circuit to the third shadow storage circuit in the first snapshot mode.

5. The integrated circuit of claim 1 further comprising:

a fourth multiplexer circuit configurable to provide the state of the output signal of the first shadow storage circuit to an input of the first data storage circuit in a user storage mode;

a third data storage circuit; and

a fifth multiplexer circuit configurable to provide a state of an output signal of the third shadow storage circuit to an input of the third data storage circuit in the user storage mode.

6. The integrated circuit of claim 1 further comprising:

a third data storage circuit;

a fourth shadow storage circuit;

a fourth multiplexer circuit coupled between an output of the third data storage circuit and an input of the fourth shadow storage circuit; and

a fifth multiplexer circuit coupled to the fourth multiplexer circuit, wherein the fifth multiplexer circuit is configurable to provide a state of an output signal of the third multiplexer circuit to the input of the third shadow storage circuit in the scan mode bypassing the second shadow storage circuit and the fourth shadow storage circuit.

7. The integrated circuit of claim 6 , wherein the fourth multiplexer circuit is configurable to provide a second data signal from the output of the third data storage circuit to the fourth shadow storage circuit in a second snapshot mode.

8. The integrated circuit of claim 1 , wherein the first and the second data storage circuits store data in response to a first clock signal, and wherein the first, the second, and the third shadow storage circuits store data in response to a second clock signal that is different from the first clock signal.

9. The integrated circuit of claim 1 further comprising:

a core logic region comprising programmable logic circuitry, wherein interconnects are configurable to couple the third shadow storage circuit to the programmable logic circuitry.

10. The integrated circuit of claim 1 further comprising:

a fourth multiplexer circuit comprising a first input coupled to an output of the second shadow storage circuit and a second input coupled to an output of the third multiplexer circuit, wherein the fourth multiplexer circuit is configurable to provide the state of the output signal of the first shadow storage circuit from the third multiplexer circuit to the input of the third shadow storage circuit in the scan mode.

11. An integrated circuit comprising:

first and second data storage circuits;

first, second, and third shadow storage circuits;

a first multiplexer circuit coupled between an output of the first shadow storage circuit and an input of the first data storage circuit;

a second multiplexer circuit coupled between an output of the second shadow storage circuit and an input of the second data storage circuit; and

a third multiplexer circuit coupled to the second multiplexer circuit, wherein the third multiplexer circuit is configurable to provide a state of an output signal of the first shadow storage circuit to an input of the third shadow storage circuit in a scan mode bypassing the second shadow storage circuit, and wherein the first multiplexer circuit is configurable to provide the state of the output signal of the first shadow storage circuit to the input of the first data storage circuit in a first user storage mode.

12. The integrated circuit of claim 11 further comprising:

a third data storage circuit; and

a fourth multiplexer circuit configurable to provide a state of an output signal of the third shadow storage circuit to an input of the third data storage circuit in the first user storage mode.

13. The integrated circuit of claim 11 further comprising:

a third data storage circuit;

a fourth shadow storage circuit;

a fourth multiplexer circuit coupled between an output of the fourth shadow storage circuit and an input of the third data storage circuit; and

a fifth multiplexer circuit coupled to the third multiplexer circuit, wherein the fifth multiplexer circuit is configurable to provide a state of an output signal of the third multiplexer circuit to the input of the third shadow storage circuit in the scan mode bypassing the second shadow storage circuit and the fourth shadow storage circuit.

14. The integrated circuit of claim 11 , wherein the second multiplexer circuit is configurable to provide a state of a signal at the output of the second shadow storage circuit to the input of the second data storage circuit in a second user storage mode that occurs at a different time than the first user storage mode.

15. The integrated circuit of claim 11 further comprising:

a core logic region comprising first and second logic circuits, wherein the output of the first shadow storage circuit is coupled to the first logic circuit, and wherein the third shadow storage circuit comprises an output that is coupled to the second logic circuit.

16. A method for reading data from configurable logic circuits, wherein the method comprises:

configuring a first multiplexer circuit to provide a state of a first data signal from a first data storage circuit to a first shadow storage circuit in a snapshot mode, wherein a second multiplexer circuit is coupled between an output of a second data storage circuit and an input of a second shadow storage circuit; and

configuring a third multiplexer circuit to provide a state of an output signal of the first shadow storage circuit to an input of a third shadow storage circuit in a scan mode bypassing the second shadow storage circuit, wherein the third multiplexer circuit is coupled to the second multiplexer circuit.

17. The method of claim 16 further comprising:

configuring a fourth multiplexer circuit to provide a state of a second data signal from a third data storage circuit to the third shadow storage circuit in the snapshot mode.

18. The method of claim 16 further comprising:

configuring a fourth multiplexer circuit to provide the state of the output signal of the first shadow storage circuit from the third multiplexer circuit to the input of the third shadow storage circuit in the scan mode bypassing the second shadow storage circuit and a fourth shadow storage circuit, wherein a fifth multiplexer circuit is coupled to an output of a third data storage circuit, an output of the fourth multiplexer circuit, and an input of the fourth shadow storage circuit.

19. The method of claim 16 further comprising:

configuring a fourth multiplexer circuit to provide the state of the output signal of the first shadow storage circuit to an input of the first data storage circuit in a user storage mode; and

configuring a fifth multiplexer circuit to provide a state of an output signal of the third shadow storage circuit to an input of a third data storage circuit in the user storage mode.

20. The method of claim 16 further comprising:

storing data in the first and the second data storage circuits in response to a first clock signal; and

storing data in the first, the second, and the third shadow storage circuits in response to a second clock signal that is different from the first clock signal during the scan mode.