Integrated circuits with programmable non-volatile resistive switch elements
View Patent ↗Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.
1. An integrated circuit, comprising:
a first logic region;
a second logic region;
a data path configured to convey signals from the first logic region to the second logic region;
a programmable resistive switch element interposed in the data path, wherein the programmable resistive switch element comprises a first non-volatile resistive element and a second non-volatile resistive element coupled in series between the first logic region and the second logic region, wherein the first non-volatile resistive element has a cathode terminal, wherein the second non-volatile resistive element has a cathode terminal that is coupled to the cathode terminal of the first non-volatile resistive element, wherein the programmable resistive switch element further comprises a programming transistor coupled to the cathode terminals of the first and second non-volatile resistive elements;
a first driver circuit configured to drive an anode terminal of the first non-volatile resistive element;
a second driver circuit configured to drive an anode terminal of the second non-volatile resistive element, wherein the first and second driver circuits are tristate buffer circuits; and
a third driver circuit configured to output a programming source signal to a source terminal of the programming transistor, wherein the third driver circuit is not a tristate buffer circuit.
2. The integrated circuit of claim 1 , further comprising:
a fourth driver circuit configured to output a programming gate signal to a gate terminal of the programming transistor.
3. The integrated circuit of claim 2 , wherein at least one of the four driver circuits is configured to apply a positive voltage to the programmable resistive switch element while at least another one of the four driver circuits is configured to apply a negative voltage of the same magnitude as the positive voltage to the programmable resistive switch element.
4. The integrated circuit of claim 1 , further comprising:
input-output circuitry formed using transistors with a first gate oxide thickness, wherein the programming transistor has a second gate oxide thickness that is less than the first gate oxide thickness.
5. The integrated circuit of claim 1 , wherein the programming transistor is formed in a semiconductor substrate, and wherein the programmable resistive switch element is formed only in selected layers of a dielectric stack on the semiconductor substrate.
6. An integrated circuit, comprising:
a first logic region;
a second logic region;
a data path configured to convey signals from the first logic region to the second logic region;
a programmable resistive switch element interposed in the data path, the programmable resistive switch element comprises a first non-volatile resistive element and a second non-volatile resistive element coupled in series between the first logic region and the second logic region, wherein the first non-volatile resistive element has a cathode terminal, wherein the second non-volatile resistive element has a cathode terminal that is coupled to the cathode terminal of the first non-volatile resistive element, wherein the programmable resistive switch element further comprises a programming transistor coupled to the cathode terminals of the first and second non-volatile resistive elements;
a driver circuit configured to drive an anode terminal of the first non-volatile resistive element;
a multiplexer having a first input configured to receive a user signal, a second input configured to receive a programming signal that is different than the user signal, and an output that is coupled to the driver circuit.
7. The integrated circuit of claim 6 , further comprising a scan chain register configured to provide the programming signal to the second input of the multiplexer.
8. The integrated circuit of claim 6 , further comprising an additional multiplexer configured to provide the programming signal to the second input of the multiplexer.
9. The integrated circuit of claim 8 , wherein the multiplexer and the additional multiplexer are both controlled by a program enable signal.
10. The integrated circuit of claim 9 , further comprising:
a lookup table coupled to a first input of the additional multiplexer; and
a scan chain register coupled to a second input of the additional multiplexer.
11. The integrated circuit of claim 10 , further comprising another multiplexer coupled between the lookup table and the scan chain register.
12. An integrated circuit, comprising:
a first logic region;
a second logic region;
a data path configured to convey signals from the first logic region to the second logic region; and
a programmable resistive switch element interposed in the data path, wherein the programmable resistive switch element comprises a first non-volatile resistive element and a second non-volatile resistive element coupled in series between the first logic region and the second logic region, wherein the first non-volatile resistive element has a cathode terminal, wherein the second non-volatile resistive element has a cathode terminal that is coupled to the cathode terminal of the first non-volatile resistive element, wherein the programmable resistive switch element further comprises a programming transistor coupled to the cathode terminals of the first and second non-volatile resistive elements, wherein the programming transistor is formed in a semiconductor substrate, wherein the programmable resistive switch element is formed only in selected layers of a dielectric stack on the semiconductor substrate, and wherein an anode terminal of the first non-volatile resistive element is formed entirely above an anode terminal of the second non-volatile resistive element in the dielectric stack.
13. The integrated circuit of claim 12 , wherein the anode terminal of the first non-volatile resistive element and the anode terminal of the second non-volatile resistive element are formed in two consecutive metal routing layers in the dielectric stack.
14. The integrated circuit of claim 12 , wherein the anode terminal of the first non-volatile resistive element is formed directly above the anode terminal of the second non-volatile resistive element in the dielectric stack.
15. The integrated circuit of claim 12 , wherein the dielectric stack comprises a single conductive structure configured as both the cathode terminal of the first non-volatile resistive element and the cathode terminal of the second non-volatile resistive element.
16. The integrated circuit of claim 15 , wherein the conductive structure is directly interposed between the anode terminal of the first non-volatile resistive element and the anode terminal of the second non-volatile resistive element in the dielectric stack.