Floating-point decomposition circuitry with dynamic precision
Circuitry for decomposing block floating-point numbers into lower precision floating-point numbers is provided. The circuitry may include a high precision storage circuit configured to provide high precision floating-point numbers, input selectors configured to receive the high precision floating-point numbers from the high precision storage circuit and to generate corresponding lower precision floating-point components with adjusted exponents, and a low precision block floating-point vector circuit configured to combine the various lower precision floating-point components generated by the input selectors. The lower precision floating-point components may be processed spatially or over multiple iterations over time.
1. Circuitry, comprising:
a storage circuit configurable to output a floating-point number having a first precision and an exponent value;
an input selection circuit comprising:
a mantissa selection circuit comprising:
an adder;
rounding logic configurable to output a rounding bit to the adder;
an overflow comparator configurable to receive signals from the adder; and
a multiplexer configurable to receive signals from the adder and signals from the overflow comparator, wherein the mantissa selection circuit is configurable to:
receive a mantissa component of the floating-point number; and
select a portion of the mantissa component of the floating-point number less than an entirety of the mantissa component of the floating-point number to produce an adjusted mantissa component having a second precision that is less than the first precision; and
an exponent selection circuit configurable to:
receive the exponent value of the floating-point number; and
subtract, from the exponent value, a value based on a mantissa width of the adjusted mantissa component to produce an adjusted exponent value based on the second precision; and
a floating-point vector circuit comprising a multiplier having a precision that is less than the first precision, wherein the multiplier is configurable to perform multiplication using the adjusted mantissa component and the adjusted exponent value from the input selection circuit.
2. The circuitry of claim 1 , wherein the storage circuit is configurable to output a second floating-point number having the first precision, and wherein the input selection circuit comprises:
a second mantissa selection circuit configurable to:
receive a mantissa component of the second floating-point number; and
select a portion of the mantissa component of the second floating-point number less than an entirety of the mantissa component of the second floating-point number to produce a second adjusted mantissa component having the second precision.
3. The circuitry of claim 2 , wherein the floating-point number and the second floating-point number have the same exponent value, and the floating-point vector circuit is configurable to:
multiply the adjusted mantissa component of the floating-point number and the second adjusted mantissa component of the second floating-point number.
4. The circuitry of claim 3 , wherein the mantissa width is equal to the precision of the multiplier.
5. The circuitry of claim 1 , wherein the floating-point vector circuit comprises a floating-point dot product engine.
6. The circuitry of claim 1 , wherein the floating-point vector circuit comprises a block floating-point dot product engine.
7. The circuitry of claim 1 , wherein the floating-point vector circuit comprises:
a plurality of multiplier circuits, wherein each multiplier circuit comprises the multiplier, respectively, wherein each multiplier is configurable to output a signal based on the adjusted mantissa component and the adjusted exponent value; and
an adder tree configurable to receive output signals from the plurality of multiplier circuits.
8. The circuitry of claim 1 , further comprising:
a precision controller configurable to generate a select signal that is fed to the input selection circuit.
9. The circuitry of claim 8 , wherein the precision controller comprises a precision cycle counter.
10. The circuitry of claim 8 , wherein the exponent selection circuit comprises:
a subtraction circuit configurable to compute a difference between the exponent value and a number that is a function of a value of the select signal.
11. The circuitry of claim 10 , wherein the exponent selection circuit further comprises:
an underflow comparator; and
a switching circuit configurable to receive the difference from the subtraction circuit, to receive an underflow signal from the underflow comparator, and to output the adjusted exponent value.
12. The circuitry of claim 11 , wherein the mantissa selection circuit is configurable to generate the adjusted mantissa component based on the underflow signal.
13. The circuitry of claim 1 , wherein the mantissa selection circuit comprises:
a multiplexing circuit having data inputs configurable to receive the adjusted mantissa component and a control input configurable to receive a select signal from a precision controller.
14. Circuitry operable to support an application, comprising:
a circuit configurable to provide a plurality of floating-point numbers having a first precision, wherein each floating-point number of the plurality of floating-point numbers comprises a mantissa component and an exponent value; and
an input selector comprising:
a plurality of mantissa selectors, wherein each mantissa selector of the plurality of mantissa selectors comprise:
an adder;
rounding logic configurable to output a rounding bit to the adder;
an overflow comparator configurable to receive signals from the adder; and
a multiplexer configurable to receive signals from the adder and signals from the overflow comparator, wherein each mantissa selector of the plurality of mantissa selectors is configurable to:
receive a first mantissa component of a first floating-point number; and
select a portion of the mantissa component of the first floating-point number less than an entirety of the first mantissa component to produce an adjusted first_mantissa component having a second precision that is less than the first precision; and
an exponent selector configurable to:
receive a first exponent value corresponding to the first floating-point number; and
subtract, from the first exponent value, a value based on a mantissa width of the adjusted mantissa component to produce an adjusted exponent value based on the second precision; and
a floating-point vector circuit comprising a plurality of multipliers respectively having a precision that is less than the first precision, wherein each multiplier of the plurality of multipliers is configurable to perform multiplication using at least one adjusted mantissa component and the adjusted exponent value from the input selector.
15. The circuitry of claim 14 , wherein the input selector is configurable to receive a select signal having a first select range when the application uses a first amount of precision and a second select range that is different than the first select range when the application uses a second amount of precision that is different than the first amount of precision, and wherein the plurality of mantissa selectors are respectively configurable to selectively round a corresponding adjusted mantissa component.
16. The circuitry of claim 15 , further comprising:
a precision cycle counter circuit configurable to generate the select signal to implement decomposition over time.
17. Circuitry, comprising:
a first group of input selectors configurable to receive first high precision floating-point numbers of a first precision and to generate corresponding first adjusted mantissa components and a first adjusted exponent value, wherein each input selector of the first group of input selectors respectively comprise:
at least one first mantissa selection circuit, wherein each first mantissa circuit comprises:
an adder;
rounding logic configurable to output a rounding bit to the adder;
an overflow comparator configurable to receive signals from the adder; and
a multiplexer configurable to receive signals from the adder and signals from the overflow comparator, wherein each of the at least one first mantissa selection circuit is configurable to:
receive a mantissa component of a respective first high floating-point number of the first high precision floating-point numbers; and
select a portion of the mantissa component less than an entirety of the mantissa component to produce a first adjusted mantissa component having a second precision that is less than the first precision; and
an exponent selection circuit configurable to:
receive a first exponent value of the respective first high precision floating- point number; and
subtract, from the first exponent value, a value based on a mantissa width of the first adjusted mantissa component to produce the first adjusted exponent value based on the second precision; and
a first lower precision floating-point matrix circuit configurable to receive the first adjusted mantissa components comprising the first adjusted mantissa component and the first adjusted exponent component from the first group of input selectors; and
a second group of input selectors configurable to receive second high precision floating- point numbers of a third precision and to generate corresponding second adjusted mantissa components and a second adjusted exponent value, wherein each input selector of the second group of input selectors respectively comprise:
at least one second mantissa selection circuit configurable to:
receive a second mantissa component of a respective second high precision floating-point number; and
select a portion of the second mantissa component less than an entirety of the second mantissa component to produce a second adjusted mantissa component of the respective second high precision floating-point number having the second precision less than the third precision; and
an exponent selection circuit configurable to:
receive a second exponent value of the second high precision floating-point numbers; and
subtract, from the second exponent value, a value based on a mantissa width of the second adjusted mantissa component to produce the second adjusted exponent value based on the second precision; and
a second lower precision floating-point matrix circuit configurable to receive the second adjusted mantissa components comprising the second adjusted mantissa component and the second adjusted exponent value from the second group of input selectors.
18. The circuitry of claim 17 , comprising:
a reduction circuit configurable to:
multiply a plurality of first adjusted mantissa components of the first high precision floating-point numbers with a plurality of second mantissa components of the second high precision floating-point numbers; and
add the first adjusted exponent value and the second adjusted exponent component.
19. The circuitry of claim 17 , wherein the first high precision floating-point numbers have the same exponent and the second high precision floating-point numbers have the same exponent, wherein the first exponent value of the first high precision floating-point numbers is different from the second exponent value of the second high precision floating-point numbers.
20. The circuitry of claim 17 , wherein each second mantissa selection circuit of the at least one second mantissa selection circuit comprises:
a second adder;
second rounding logic configurable to output a second rounding bit to the second adder;
a second overflow comparator configurable to receive signals from the second adder; and
a second multiplexer configurable to receive signals from the second adder and signals from the second overflow comparator.