Specialized processing blocks with fixed-point and floating-point structures

1. An integrated circuit, comprising:

a specialized processing block that comprises:

a multiplier network that generates redundant form output vectors;

a compressor that receives the redundant form output vectors from the multiplier network and that also receives additional vectors, wherein:

during a fixed-point mode, the compressor selectively uses the additional vectors to generate an output of the compressor; and

during a floating-point mode, a first portion of the redundant form output vectors bypasses the compressor while a second portion of the redundant form output vectors is routed through the compressor to obtain a floating-point output, and the compressor provides a value of zero at a rounding position of the floating-point output; and

a carry propagate adder that receives the first bypassed portion of the redundant form output vectors and the floating-point output from the compressor during the floating-point mode.

2. The integrated circuit of claim 1 , wherein the compressor provides the value of zero at a least significant bit position of the second portion of the redundant form output vectors.

3. The integrated circuit of claim 1 , wherein the compressor comprises a 3:2 compressor circuit.

4. The integrated circuit of claim 1 , wherein the compressor comprises a 4:2 compressor circuit.

5. The integrated circuit of claim 1 , wherein the carry propagate adder comprises:

a first adder that receives the first portion of the redundant form output vectors; and

a second adder that receives the floating-point output from the compressor.

6. The integrated circuit of claim 5 , wherein the second adder contains prefix networks.

7. The integrated circuit of claim 6 , wherein the prefix networks in the second adder includes a level-zero prefix network that receives only a subset of the floating-point output.

8. The integrated circuit of claim 7 , wherein the second adder further includes:

redundant least significant bit (LSB) processing logic circuits that only receive another subset of the floating-point output.

9. The integrated circuit of claim 8 , wherein the redundant LSB processing logic circuits comprises:

an AND gate for outputting a generate LSB; and

an OR gate for outputting a propagate LSB, wherein the OR gate receives a floating-point control signal.

10. The integrated circuit of claim 8 , wherein the prefix networks in the second adder further comprises:

a first reduced prefix network that receives signals from the level-zero prefix network;

a second reduced prefix network that receives signals from the level-zero prefix network and the redundant LSB processing logic circuits; and

a third prefix network that receives signals from the first and second reduced prefix networks.

11. The integrated circuit of claim 10 , wherein the second adder is configured to output a sum output, a sum-plus-1 output, and a sum-plus-2 output.

12. A method of operating a specialized processing block, comprising:

with a multiplier pipeline in the specialized processing block, generating redundant form outputs;

with a compressor circuit in the specialized processing block, receiving the redundant form outputs and first and second non-redundant form outputs, wherein the compressor circuit receives the first non-redundant form output at a first input terminal of the compressor and the second non-redundant form output at a second input terminal of the compressor that is separate from the first input terminal;

during a fixed-point mode, using the compressor circuit to process the first and second non-redundant form outputs; and

during a floating-point mode, using the compressor circuit to process only the redundant form outputs.

13. The method of claim 12 , further comprising:

with a carry propagate adder in the specialized processing block, receiving processed signals from the compressor circuit and the multiplier pipeline; and

routing at least a portion of the redundant form outputs to bypass the compressor circuit during the floating-point mode.

14. The method of claim 13 , wherein the carry propagate adder includes a first adder that generates a fixed-point output and a second adder that generates a floating-point output, the method further comprising:

with a level-zero prefix structure in the second adder, receiving a first subset of the redundant form outputs; and

with redundant least significant bit (LSB) processing circuitry in the second adder, receiving a second subset of the redundant form outputs.

15. The method of claim 14 , further comprising:

with additional parallel prefix structures in the second adder, receiving signals from the level-zero prefix structure and redundant LSB processing circuitry and outputting a sum output, a sum-plus-1 output, and a sum-plus-2 output.

16. An integrated circuit, comprising:

a digital signal processor that comprises:

partial product generation circuits;

a compressor circuit that receives signals from the partial product generation circuits;

a carry propagate adder circuit that receives signals from the compressor circuit; and

multi-channel accumulation circuitry interposed in a feedback path connecting the carry propagate adder circuit back to an input of the compressor circuit.

17. The integrated circuit of claim 16 , wherein the digital signal processor is operable in a fixed-point arithmetic mode of operation and in a floating-point arithmetic mode of operation.

18. The integrated circuit of claim 16 , wherein the multi-channel accumulation circuitry includes at least two accumulation registers and a multiplexer for selectively bypassing one of the two accumulation registers.

19. The integrated circuit of claim 16 , wherein the multi-channel accumulation circuitry comprises a first-in first-out (FIFO) circuit.

20. The integrated circuit of claim 16 , wherein the multi-channel accumulation circuitry comprises data storage circuitry interposed in the feedback path.