Coarse-grain programmable routing network for logic devices
Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable coarse-grain routing network may be implemented on an active interposer die. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. A protocol-based network on chip (NoC) may be overlaid on the coarse-grain routing network. Although the NoC protocol is nondeterministic, the coarse-grain routing network includes an array of programmable switch boxes linked together using a predetermined number of routing channels to provide deterministic routing. Pipeline registers may be interposed within the routing channels at fixed locations to guarantee timing closure.
1. Circuitry, comprising:
a first circuit that includes fine-grain routing wires; and
a second circuit that includes a coarse-grain routing network having a plurality of channels forming a deterministic routing path, wherein a first portion of the plurality of channels is used for data payload and wherein a second portion of the plurality of channels is configured to implement an interconnect backpressure mechanism.
2. The circuitry of claim 1 , wherein the first circuit is physically mounted above the second circuit.
3. The circuitry of claim 1 , wherein the second portion of the plurality of channels that implements the interconnect backpressure mechanism is further configured to convey backpressure credit bits.
4. The circuitry of claim 1 , wherein the second portion of the plurality of channels that implements the interconnect backpressure mechanism is further configured to convey a data valid bit.
5. The circuitry of claim 1 , wherein the second portion of the plurality of channels is further configured to send timestamp information deterministically.
6. The circuitry of claim 1 , wherein the second portion of the plurality of channels is further configured to support debugging operations.
7. Circuitry, comprising:
a first die that comprises fine-grain routing wires configured to provide a first level of routing granularity; and
a second die that comprises a coarse-grain routing network configured to provide a second level of routing granularity that is different than the first level of routing granularity, wherein the coarse-grain routing network is further configured at run-time using control signals generated by the first die.
8. The circuitry of claim 7 , wherein the first die further comprises programmable logic circuitry configured to generate the control signals.
9. The circuitry of claim 7 , wherein the first die further comprises a finite state machine configured to generate the control signals.
10. The circuitry of claim 7 , wherein the first die further comprises a soft processor configured to generate the control signals.
11. The circuitry of claim 7 , wherein the first die further comprises a microcontroller configured to generate the control signals.
12. The circuitry of claim 7 , wherein the coarse-grain routing network comprises a multiplexing circuit having a first data input configured to receive the control signals.
13. The circuitry of claim 12 , wherein the multiplexing circuit has a second data input configured to receive signals from a configuration memory cell.
14. The circuitry of claim 13 , wherein the multiplexing circuit has a third data input configured to receive signals from a counter.
15. The circuitry of claim 7 , wherein the coarse-grain routing network comprises channels configured using a fixed bandwidth allocation.
16. The circuitry of claim 7 , wherein the coarse-grain routing network comprises channels configured using a dynamically-scheduled bandwidth allocation.
17. Circuitry, comprising:
a first circuit that includes fine-grain routing wires; and
a second circuit that includes a coarse-grain routing network having a plurality of channels forming a deterministic routing path.
18. The circuitry of claim 17 , wherein the deterministic routing path exhibits guaranteed timing closure.
19. The circuitry of claim 17 , wherein global routing for the first circuit is performed using the coarse-grain routing network in the second circuit.
20. The circuitry of claim 17 , wherein the coarse-grain routing network comprises pipeline registers at fixed locations on the second circuit, and wherein register pipelining on the first circuit is adjustable.