Innovative interconnect design for package architecture to improve latency
An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.
1. An integrated circuit package comprising:
a package substrate comprising an interconnect bridge, a first electrical trace, and a second electrical trace, wherein the first and second electrical traces are located in the interconnect bridge;
a first die, mounted on the package substrate, and comprising a first input-output (IO) package connector and a second IO package connector that have a first pitch; and
a second die, mounted on the package substrate, and comprising a third IO package connector and a fourth IO package connector that have a second pitch, wherein the first and second pitches are different pitches, wherein the first electrical trace couples the first and the third IO package connectors, and wherein the second electrical trace couples the second and the fourth IO package connectors.
2. The integrated circuit package of claim 1 , wherein the first electrical trace comprises a first turn and a second turn in a lateral plane of the interconnect bridge, and wherein the second electrical trace comprises a third turn and a fourth turn in the lateral plane of the interconnect bridge, and wherein the first, second, third, and fourth turns are perpendicular turns.
3. The integrated circuit package of claim 2 wherein a portion of the first electrical trace is below a portion of the second electrical trace in the interconnect bridge.
4. The integrated circuit package of claim 1 , wherein each of the first and the second electrical traces has a step shape.
5. The integrated circuit package of claim 1 , wherein the first die is a processing die.
6. The integrated circuit package of claim 1 , wherein the first die is a configurable die.
7. The integrated circuit package of claim 6 , wherein the second die is a transceiver die.
8. An integrated circuit package comprising:
a package substrate comprising a first electrical trace and a second electrical trace;
a first die and a second die that are mounted on the package substrate and arranged in a first row; and
a third die and a fourth die that are mounted on the package substrate and arranged in a second row, wherein the first electrical trace couples the first and the fourth dies, wherein the second electrical trace couples the second and the third dies, and wherein each of the first electrical trace and the second electrical trace has a step shape.
9. The integrated circuit package of claim 8 , wherein the first and the third dies are arranged in a first column, and wherein the second and the fourth dies are arranged in a second column.
10. The integrated circuit package of claim 8 , wherein the first electrical trace and the second electrical trace are step-cross traces.
11. The integrated circuit package of claim 8 , wherein the package substrate comprises an interconnect bridge that comprises the first and the second electrical traces.
12. The integrated circuit package of claim 11 , wherein the first electrical trace comprises a first turn and a second turn in a lateral plane of the interconnect bridge, and the second electrical trace comprises a third turn and a fourth turn in the lateral plane of the interconnect bridge, and wherein the first, the second, the third, and the fourth turns are perpendicular turns.
13. The integrated circuit package of claim 8 , wherein the package substrate further comprises a third electrical trace and a fourth electrical trace, wherein the third electrical trace couples the first and the third dies, and wherein the fourth electrical trace couples the second and the fourth dies.
14. The integrated circuit package of claim 13 , wherein the package substrate further comprises a fifth electrical trace and a sixth electrical trace, wherein the fifth electrical trace couples the first and the second dies, and wherein the sixth electrical trace couples the third and the fourth dies.
15. The integrated circuit package of claim 8 , wherein the first, the second, the third, and the fourth dies are configurable dies.
16. An integrated circuit package comprising:
a package substrate comprising a first electrical trace and a second electrical trace;
a first die and a second die that are mounted on the package substrate and arranged in a first row; and
a third die and a fourth die that are mounted on the package substrate and arranged in a second row, wherein the first electrical trace couples the first and the fourth dies, wherein the second electrical trace couples the second and the third dies, wherein the first electrical trace comprises a first turn and a second turn in a lateral plane of the package substrate, wherein the second electrical trace comprises a third turn and a fourth turn in the lateral plane of the package substrate, and wherein the first, the second, the third, and the fourth turns are perpendicular turns.
17. The integrated circuit package of claim 16 , wherein the first electrical trace and the second electrical trace are step-cross traces.
18. The integrated circuit package of claim 16 , wherein the package substrate further comprises an interconnect bridge that comprises the first and the second electrical traces.
19. The integrated circuit package of claim 16 , wherein the first and the third dies are arranged in a first column, and wherein the second and the fourth dies are arranged in a second column.
20. The integrated circuit package of claim 16 , wherein the package substrate further comprises a third electrical trace and a fourth electrical trace, wherein the third electrical trace couples the first and the third dies, and wherein the fourth electrical trace couples the second and the fourth dies.