Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling same
Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.
1. A semiconductor apparatus, comprising:
a first semiconductive device including an active surface and a backside surface;
a through-silicon via (TSV) that communicates from the active surface to the backside surface;
first and second electrical bumps coupled to the active surface;
subsequent and second semiconductive devices in respective contact with the first and second electrical bumps, wherein the subsequent and second semiconductive devices are positioned face-to-face with the first semiconductive device; and
a redistribution layer (RDL) including at least one inner via in direct contact with the first semiconductive device backside surface and the TSV.
2. The semiconductor apparatus of claim 1 , wherein the TSV is a first TSV and wherein the first TSV is positioned below the subsequent semiconductive device, further including:
a second TSV that communicates from the active surface to the backside surface, wherein the second TSV is positioned below the second semiconductive device.
3. The semiconductor apparatus of claim 1 , wherein the first semiconductive device exhibits a die shadow, and wherein the RDL is configured substantially within the die shadow.
4. The semiconductor apparatus of claim 1 , wherein the first semiconductive device exhibits a die shadow, wherein the RDL is configured substantially within the die shadow, and wherein each of the subsequent, and second semiconductive devices are configured within the die shadow.
5. The semiconductor apparatus of claim 1 , wherein the first and second electrical bumps are copper pillars.
6. The semiconductor apparatus of claim 1 , wherein each of the subsequent and second semiconductive devices include active and backside surfaces, wherein the first, and second electrical bumps are copper pillars that contact the first semiconductive device active surface to the respective subsequent, and second semiconductive device active surfaces.
7. The semiconductor apparatus of claim 1 , wherein each of the subsequent and second semiconductive devices include active and backside surfaces, further including a heat sink seated on the respective subsequent and second semiconductive device backside surfaces.
8. The semiconductor apparatus of claim 1 , further including a molding compound that contacts the respective first and second electrical bumps.
9. The semiconductor apparatus of claim 1 , wherein the subsequent and second semiconductive devices are configured within a die shadow of the first semiconductive device, and wherein the RDL is configured within the die shadow.
10. The semiconductor apparatus of claim 1 , further including:
a molding compound that contacts the respective first, and second electrical bumps, wherein the first and second electrical bumps are copper pillars;
wherein the TSV is a first TSV and wherein the first TSV is positioned below the subsequent semiconductive device;
a second TSV that communicates from the active surface to the backside surface, wherein the second TSV is positioned below the second semiconductive device;
wherein the first semiconductive device exhibits a die shadow, wherein the RDL is configured substantially within the die shadow, and wherein each of the subsequent and second semiconductive devices are configured within the die shadow;
a heat sink seated on the respective subsequent and second semiconductive device backside surfaces.
11. The semiconductor apparatus of claim 1 , wherein the TSV is one of a plurality of TSVs, and wherein the plurality of TSVs are asymmetrically configured within the first semiconductive device.
12. The semiconductor apparatus of claim 1 , further including third semiconductive device face-to-face coupled to the first semiconductive device.
13. The semiconductor apparatus of claim 1 , further including:
a third semiconductive device face-to-face coupled to the first semiconductive device;
wherein the TSV is a first TSV and wherein the first TSV is positioned below the subsequent semiconductive device;
a second TSV that communicates from the active surface to the backside surface, wherein the second TSV is positioned below the second semiconductive device;
a third TSV that communicates from the active surface to the backside surface, wherein the third TSV is positioned below the third semiconductive device; and
wherein the first semiconductive device exhibits a die shadow, and wherein the RDL is configured substantially within the die shadow.
14. The semiconductor apparatus of claim 1 , further including:
a third semiconductive device face-to-face coupled to the first semiconductive device;
wherein the TSV is a first TSV and wherein the first TSV is positioned below the subsequent semiconductive device;
a second TSV that communicates from the active surface to the backside surface, wherein the second TSV is positioned below the second semiconductive device;
a third TSV that communicates from the active surface to the backside surface, wherein the third TSV is positioned below the third semiconductive device;
wherein the first semiconductive device exhibits a die shadow, and wherein the RDL is configured substantially within the die shadow; and
wherein the subsequent, second and third semiconductive devices are substantially within the die shadow.
15. A computing system, comprising:
a first semiconductive device including an active surface and a backside surface;
a through-silicon via (TSV) that communicates from the active surface to the backside surface;
first and second electrical bumps coupled to the active surface;
subsequent and second semiconductive devices in respective contact with the first and second electrical bumps, wherein the subsequent and second semiconductive devices are positioned face-to-face with the first semiconductive device;
a redistribution layer (RDL) including at least one inner via in direct contact with the first semiconductive device backside surface and the TSV;
a molding compound that contacts the respective first and second electrical bumps, wherein the first and second electrical bumps are copper pillars;
wherein the TSV is a first TSV and wherein the first TSV is positioned below the subsequent semiconductive device;
a second TSV that communicates from the active surface to the backside surface, wherein the second TSV is positioned below the second semiconductive device;
wherein the first semiconductive device exhibits a die shadow, wherein the RDL is configured substantially within the die shadow, and wherein each of the subsequent and second semiconductive devices are configured within the die shadow; and
wherein the semiconductor apparatus is part of a chipset.
16. The computing system of claim 15 , further including:
a heat sink seated on the respective subsequent and second semiconductive device backside surfaces; and
a ball-grid array contacting the RDL, RDL is coupled to a board, and wherein the board includes a shell that provides electrical insulation for the first semiconductive device.
17. A semiconductor apparatus, comprising:
a first semiconductive device including an active surface and a backside surface;
a first throutth-silicon via (TSV) that communicates from the active surface to the backside surface;
a second TSV that communicates from the active surface to the backside surface, wherein the first TSV is positioned below a subsequent semiconductive device, and wherein the second TSV is positioned below a second semiconductive device;
first and second electrical bumps coupled to the active surface;
the subsequent and second semiconductive devices in respective contact with the first and second electrical bumps, wherein the subsequent and second semiconductive devices are positioned face-to-face with the first semiconductive device;
a redistribution layer (RDL) including at least one inner via in direct contact with the first semiconductive device backside surface and the first and second TSVs; and
wherein the first semiconductive device exhibits a die shadow, wherein the RDL is configured substantially within the die shadow, and wherein each of the subsequent and second semiconductive devices are configured within the die shadow.
18. The semiconductor apparatus of claim 17 , further including:
a third electrical bump coupled to the first semiconductive device active surface:
a third semiconductive device in contact with the third electrical bump, wherein the third semiconductive device is positioned face-to-face with the first semiconductive device;
a third TSV that communicates from the active surface to the backside surface, wherein the third TSV is positioned below the third semiconductive device, and wherein the third semiconductive device is within the die shadow.
19. The semiconductor apparatus of claim 18 , further including a molding compound that contacts the respective first, second and third electrical bumps.
20. The semiconductor apparatus of claim 19 , wherein the first TSV, the second TSV and the third TSV are asymmetrically configured within the first semiconductive device.
21. The semiconductor apparatus of claim 19 , wherein the first TSV, the second TSV and the third TSV are substantially uniformly distributed across the first die below the respective subsequent, second and third dice.