Methods for using a multiplier circuit to support multiple sub-multiplications using bit correction and extension
Integrated circuits with digital signal processing (DSP) blocks are provided. A DSP block may include one or more large multiplier circuits. A large multiplier circuit such as an 18×18 multiplier circuit may be used to support two or more smaller multiplication operations such as two 8×8 integer multiplications or two 9×9 integer multiplications. To implement the two 8×8 or 9×9 unsigned/signed multiplications, the 18×18 multiplier may be configured to support two 8×8 multiplications with one shared operand, two 6×6 multiplications without any shared operand, or two 7×7 multiplications without any shared operand. Any potential overlap of partial product terms may be subtracted out using correction logic. The multiplication of the remaining most significant bits can be computed using associated multiplier extension logic and appended to the other least significant bits using merging logic.
1. An integrated circuit, comprising:
a multiplier circuit having a first input, a second input, and an output, wherein:
a first sub-multiplier and a second sub-multiplier are extracted from the multiplier circuit;
the first input of the multiplier circuit is configured to receive a first input operand for the first sub-multiplier and also a first input operand for the second sub-multiplier, wherein the first input operand for the first sub-multiplier and the first input operand for the second sub-multiplier are concatenated using one or more zeroes;
the second input of the multiplier circuit is configured to receive a common input operand for the first and second sub-multipliers;
the first input operand for the first sub-multiplier and the common input operand are used to generate a first logical multiplier product internal to the multiplier circuit;
the first input operand for the second sub-multiplier and the common input operand are used to generate a second logical multiplier product internal to the multiplier circuit;
the first logical multiplier product at least partially overlaps with the second logical multiplier product; and
output bits are generated at the output of the multiplier circuit; and
an additional multiplier circuit configured to compute a correction value, wherein the correction value is applied to the output bits to obtain final multiplier output values for the first and second sub-multipliers.
2. The integrated circuit of claim 1 , wherein the multiplier circuit is unsigned, and wherein the first and second sub-multipliers are unsigned.
3. The integrated circuit of claim 1 , wherein the second input that receives the common input operand is signed.
4. The integrated circuit of claim 3 , wherein the first input of the multiplier circuit is signed, but wherein the first input operand for the first sub-multiplier and the first input operand for the second sub-multiplier are unsigned.
5. The integrated circuit of claim 3 , wherein the first input of the multiplier circuit is unsigned, and wherein the first input operand for the first sub-multiplier and the first input operand for the second sub-multiplier are unsigned.
6. The integrated circuit of claim 3 , wherein the first input of the multiplier circuit is signed, wherein the first input operand for the first sub-multiplier is signed, and wherein the first input operand for the second sub-multiplier is unsigned.
7. The integrated circuit of claim 1 , wherein some error still exists in the final multiplier output value for the first sub-multiplier even after the correction value has been applied.
8. The integrated circuit of claim 1 , wherein the additional multiplier circuit comprises a partial least significant bit (LSB) multiplier circuit.
9. The integrated circuit of claim 1 , further comprising a subtraction circuit configured to apply the correction value to the output bits to obtain the final multiplier output values for the first and second sub-multipliers.
10. An integrated circuit, comprising:
a multiplier circuit having a first input, a second input, and an output, wherein:
a first sub-multiplier and a second sub-multiplier are extracted from the multiplier circuit;
the first input of the multiplier circuit is configured to receive a combined value based on a concatenation of a first input operand for the first sub-multiplier and a first input operand for the second sub-multiplier and a sign extension of the first input operand for the second sub-multiplier;
the second input of the multiplier circuit is configured to receive a common input operand for the first and second sub-multipliers; and
output bits are generated at the output of the multiplier circuit; and
an additional multiplier circuit configured to compute a correction value, wherein the correction value is applied to the output bits to obtain final multiplier output values for the first and second sub-multipliers.
11. The integrated circuit of claim 10 , wherein the combined value is equal to the sum of the concatenation and the sign extension of the first input operand for the second sub-multiplier.
12. The integrated circuit of claim 10 , wherein the combined value is equal to the difference of the concatenation and the sign extension of the first input operand for the second sub-multiplier.
13. The integrated circuit of claim 10 , further comprising a subtraction circuit configured to apply the correction value to the output bits to obtain the final multiplier output values for the first and second sub-multipliers, wherein at least one bit output from the subtraction circuit is fed back as an input.
14. An integrated circuit, comprising:
a multiplier circuit having a first input, a second input, and an output, wherein:
the multiplier circuit is used to support a first sub-multiplier and a second sub-multiplier;
the first input is configured to receive a concatenation of a lower portion of a first input operand for the first sub-multiplier and a lower portion of a first input operand for the second sub-multiplier;
the second input is configured to receive a concatenation of a lower portion of a second input operand for the first sub-multiplier and a lower portion of a second input operand for the second sub-multiplier; and
output bits generated at the output of the multiplier circuit;
multiplier extension logic configured to receive upper portions of the first and second input operands for the first sub-multiplier and upper portions of the first and second input operands for the second sub-multiplier; and
adder circuits configured to combine the output bits with bits generated from the multiplier extension logic to obtain final multiplier output values for the first and second sub-multipliers.
15. The integrated circuit of claim 14 , wherein:
the lower portion of the first input operand for the first sub-multiplier and the lower portion of the second input operand for the first sub-multiplier are used to generate a first logical multiplier product;
the lower portion of the first input operand for the first sub-multiplier and the lower portion of the second input operand for the second sub-multiplier are used to generate a second logical multiplier product;
the lower portion of the first input operand for the second sub-multiplier and the lower portion of the second input operand for the first sub-multiplier are used to generate a third logical multiplier product; and
the first logical multiplier product at least partially overlaps with the sum of the second and third logical multiplier products.
16. The integrated circuit of claim 15 , further comprising a logic gate configured to generate at least one error bit to compensate for the overlap.
17. The integrated circuit of claim 16 , further comprising a subtraction circuit configured to subtract the at least one error bit from a sum value generated by the adder circuits to obtain the final multiplier output value for the first sub-multiplier.
18. The integrated circuit of claim 15 , further comprising:
an additional multiplier configured to compute correct least significant bits (LSBs) in the final multiplier output value for the first sub-multiplier;
a comparison circuit configured to compare the correct LSBs with a first portion of the output bits generated by the multiplier circuit; and
a subtraction circuit configured to subtract an error bit from a second portion of the output bits in response to determining that the first portion of the output bits is less than the correct LSBs.
19. The integrated circuit of claim 14 , wherein the most significant bits in the final multiplier output value for the second sub-multiplier are corrected, and wherein the least significant bits in the final multiplier output value for the first sub-multiplier are not corrected.
20. The integrated circuit of claim 14 , wherein the least significant bits in the final multiplier output value for the first sub-multiplier are partially corrected such that some error still exists in the final multiplier output value for the first sub-multiplier even after the correction.
21. The integrated circuit of claim 14 , wherein the multiplier circuit is unsigned, and wherein the multiplier extension logic is also unsigned.
22. The integrated circuit of claim 14 , wherein the multiplier circuit is signed, and wherein the multiplier extension logic is also signed.