High precision decomposable DSP entity

1. A digital signal processing (DSP) block comprising:

a plurality of multipliers; and

a summation block separate from the plurality of multipliers, wherein:

the DSP block is configurable to perform a first multiplication operation to determine a first product of a first floating-point value and a second floating-point value using only a first multiplier of the plurality of multipliers; and

the DSP block is configurable to perform a second multiplication operation between a third floating-point value and a fourth floating-point value by:

receiving, at each of the plurality of multipliers, two integer values generated from the third floating-point value and the fourth floating-point value;

generating, via the plurality of multipliers, a plurality of subproducts by multiplying, at each of the multipliers, the two integer values; and

generating a second product of the second multiplication operation by adding, via the summation block, the plurality of subproducts.

2. The DSP block of claim 1 , wherein:

the first floating-point value and the second floating-point value are single precision floating-point values; and

the third floating-point value and the fourth floating-point value are double precision floating-point values.

3. The DSP block of claim 2 , comprising a multiplexer network configurable to route the two values to each of the multipliers of the plurality of multipliers.

4. The DSP block of claim 3 , wherein:

the plurality of multipliers comprises:

a first multiplier configurable to:

receive a first upper half of the third floating-point value and a second upper half of the fourth floating-point value; and

generate a first subproduct of the plurality of subproducts by multiplying the first upper half and the second upper half;

a second multiplier configurable to:

receive a first lower half of the third floating-point value and the second upper half of the fourth floating-point value; and

generate a second subproduct of the plurality of subproducts by multiplying the first lower half and the second upper half;

a third multiplier configurable to:

receive the first upper half of the third floating-point value and a second lower half of the fourth floating-point value; and

generate a third subproduct of the plurality of subproducts by multiplying the first upper half and the second lower half; and

a fourth multiplier configurable to:

receive the first lower half of the third floating-point value and the second lower half of the fourth floating-point value; and

generate a fourth subproduct of the plurality of subproducts by multiplying the first lower half and the second lower half.

5. The DSP block of claim 2 , wherein the DSP block is configurable to generate the second product of the second multiplication operation by:

adding, via the summation block, first exponent bits of the third floating-point value and second exponent bits of the fourth floating-point value to generate a first sum; and

generating a floating-point value based on a sum of the plurality of subproducts and the first sum.

6. The DSP block of claim 1 , wherein the DSP block is configurable to perform complex math operations involving eight values that are each less precise than the third floating-point value and the fourth floating-point value.

7. The DSP block of claim 1 , comprising:

a register configurable to store a third product; and

a second summation block configurable to:

generate a sum by adding the second product and the third product; and

send the sum to the register for storage.

8. The DSP block of claim 1 , wherein the DSP block is configurable to:

receive an output of a second DSP block that is communicatively coupled to the DSP block; and

add, using second summation block of the DSP block, the second product and the output received from the second DSP block.

9. The DSP block of claim 1 , wherein the DSP block is included within a field-programmable gate array (FPGA).

10. An integrated circuit device comprising a digital signal processing (DSP) block, wherein the DSP block comprises:

a plurality of multipliers; and

a summation block separate from the plurality of multipliers, wherein:

the DSP block is configurable to perform a first multiplication operation to determine a first product of a first floating-point value and a second floating-point value using only a first multiplier of the plurality of multipliers; and

the DSP block is configurable to perform a second multiplication operation between a third floating-point value and a fourth floating-point value by:

receiving, at each of the plurality of multipliers, two integer values generated from the third floating-point value and the fourth floating-point value;

generating, via the plurality of multipliers, a plurality of subproducts by multiplying, at each of the multipliers, the two integer values;

receiving, at the summation block, the plurality of subproducts, first exponent bits of the third floating-point value, and second exponent bits of the fourth floating-point value;

generating, via the summation block, a first sum by adding the plurality of subproducts;

generating, via the summation block, a second sum by adding the first exponent bits and the second exponent bits; and

generating a second product of the second multiplication operation based on the first sum and the second sum.

11. The integrated circuit device of claim 10 , wherein the DSP block is configurable to perform the first product by:

receiving, at the first multiplier, first mantissa bits of the first floating-point value, second mantissa bits of the second floating-point value, third exponent bits of the first floating-point value, and fourth exponent bits of the second floating-point value;

generating, using multiplier circuitry of the first multiplier, a third product based on the first mantissa bits of the first floating-point value and the second mantissa bits of the second floating-point value;

generating, using adder circuitry of the first multiplier, a third sum by adding the third exponent bits and the fourth exponent bits; and

generating the first product based on the third product and the third sum.

12. The integrated circuit device of claim 10 , the DSP block comprises a multiplexer network configurable to:

generate the two integer values from the third floating-point value and the fourth floating-point value; and

route the two integer values to the plurality of multipliers.

13. The integrated circuit device of claim 10 , wherein the summation block comprises a combining block configurable to generate the second product.

14. The integrated circuit device of claim 10 , wherein the DSP block is configurable to perform multiplication operations involving fixed-point values.

15. The integrated circuit device of claim 10 , comprising a second DSP block communicatively coupled to the DSP block, wherein the DSP block is configurable to:

receive an output of the second DSP block; and

add, using a second summation block of the DSP block, the second product and the output received from the second DSP block.

16. The integrated circuit device of claim 15 , wherein the output of the second DSP block comprises a double precision floating-point value generated by the second DSP block by performing a third multiplication operation between a fifth double precision floating-point value and a sixth double precision floating-point value.

17. The integrated circuit device of claim 10 , wherein the plurality of multipliers is configurable to simultaneously perform multiplication involving a first number of bits, wherein the first number of bits is greater than a number of bits the DSP block is configurable to receive in a single clock cycle.

18. A system comprising:

an integrated circuit device; and

a programmable logic device communicatively coupled to the integrated circuit device, wherein the programmable logic device comprises a digital signal processing (DSP) block that comprises:

a plurality of multipliers; and

a summation block separate from the plurality of multipliers, wherein:

the DSP block is configurable to perform a first multiplication operation to determine a first product of a first floating-point value and a second floating-point value using only a first multiplier of the plurality of multipliers; and

the DSP block is configurable to perform a second multiplication operation between a third floating-point value and a fourth floating-point value by:

receiving, at each of the plurality of multipliers, two integer values generated from the third floating-point value and the fourth floating-point value;

generating, via the plurality of multipliers, a plurality of subproducts by multiplying, at each of the multipliers, the two integer values;

receiving, at the summation block, the plurality of subproducts, first exponent bits of the third floating-point value, and second exponent bits of the fourth floating-point value;

generating, via the summation block, a first sum by adding the plurality of subproducts;

generating, via the summation block, a second sum by adding the first exponent bits and the second exponent bits; and

generating a second product of the second multiplication operation based on the first sum and the second sum.

19. The system of claim 18 , comprising a substrate, wherein the integrated circuit device and the programmable logic device are mounted on the substrate.

20. The system of claim 19 , wherein the programmable logic device comprises a field-programmable gate array (FPGA).